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pci 6520cb data book preliminary

pci 6520cb data book version 2.0 may 2004 website : http://www.plxtech.com technical support : http://www.plxtech.com/support/ phone : 408 774-9060 800 759-3735 fax : 408 774-2169 preliminary
? 2004 plx technology, inc. all rights reserved. plx technology, inc., retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx products. this device is not designed, intended, authorized, or warranted to be suitable for use in medical or life-support applications, devices, or systems, or other critical applications. plx technology and the plx logo are registered trademarks and fastlane is a trademark of plx technology, inc. hypertransport is a trademark of the hypertransport technology consortium. other brands and names are the property of their respective owners. order number: pci 6520cb-sil-db-p1-2.0 printed in the usa, may 2004 preliminary
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary v contents figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii supplemental documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii data assignment conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii feature summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1. company and product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2. fastlane pci 6000 bridge series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1. pci 6520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3. feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.1. multiple device expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1. general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2. write transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3. read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2. pull-up and pull-down resistor recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1. pci bus interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2. clock-related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.3. reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.4. jtag/boundary scan pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.5. serial eeprom pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.6. gpio pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.7. miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.8. system voltage pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3. power supply de-coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1. primary and secondary clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2. secondary clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1. disabling secondary clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.2. secondary clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3. using an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.4. frequency division options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.5. running secondary port faster than primary port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.6. pll and clock jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
contents pci 6520cb data book, version 2.0 vi preliminary ? 2004 plx technology, inc. all rights reserved. 4.7. detecting pci bus speed with the reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.8. primary or secondary clock frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 5. reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1. pci-xcap connections and operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1. primary port pci-xcap connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2. secondary port pci-xcap connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. secondary bus mode and frequency initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3. conventional pci mode 66 mhz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4.1. power good reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4.2. primary reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4.3. secondary reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4.4. jtag reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.5. software resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.6. power management internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.7. reset inputs effect on pci 6520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.8. pin states during pwrgd and primary reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5. register initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.5.1. default initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.5.2. serial eeprom initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.5.3. host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 6. registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1. pci configuration register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1. pci type 1 header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2. device-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.1.2.1. chip, diagnostic, and arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.1.2.2. primary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.1.2.3. timeout control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.1.2.4. miscellaneous options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.1.2.5. prefetch control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.1.2.6. secondary flow-through control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.1.2.7. buffer and internal arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.1.2.8. test and serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.1.2.9. timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.1.2.10. primary system error event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.1.2.11. gpio[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.1.2.12. clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.1.2.13. primary system error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 6.1.2.14. clock run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.1.2.15. private memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6.1.2.16. read-only register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.1.2.17. gpio[7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6.1.2.18. extended and smart prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 6.1.2.19. power management capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6.1.2.20. vpd capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6.1.2.21. pci-x capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 7. serial eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2. serial eeprom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3. serial eeprom autoload mode at reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.4. serial eeprom data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4.1. serial eeprom address and corresponding pci 6520 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
contents pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary vii 8. pci bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1. conventional pci transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2. single address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3. dual address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4. device select (devsel#) generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5. data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5.1. posted write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5.2. memory write and invalidate transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5.3. delayed write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5.4. write transaction address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.5. buffering multiple write transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.6. read transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.7. prefetchable read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.8. non-prefetchable read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.9. read prefetch address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.10. delayed read requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.11. delayed read completion with target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.12. delayed read completion on initiator bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.13. configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.14. pci 6520 type 0 access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.15. type 1-to-type 0 translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.16. type 1-to-type 1 forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.5.17. special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6. conventional pci mode transaction termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.1. pci 6520-initiated master termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.2. master abort received by pci 6520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3. target termination received by pci 6520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3.1. posted write target termination response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.6.3.2. delayed write target termination response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.6.3.3. delayed read target termination response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.6.4. pci 6520-initiated target termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.6.4.1. target retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.6.4.2. target disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.6.4.3. target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 9. pci-x bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2. general bus rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1. initiator rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.2. target rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.3. bus arbitration rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.4. configuration transaction rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.5. parity error rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.6. bus data width rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.7. split transaction rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3. pci-x sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.4. adb and buffer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5. dependencies between ad and cbe buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6. pci-x command encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.7. attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.8. burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.8.1. burst write and split completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.8.2. burst read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.9. dword transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.10. device select timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.11. wait states and target initial latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
contents pci 6520cb data book, version 2.0 viii preliminary ? 2004 plx technology, inc. all rights reserved. 9.12. split transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.12.1. split completion transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.12.2. immediate completion by the completer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.12.3. split completion address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.12.4. completer attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.12.5. split completion acceptance requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.12.6. split completion messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.13. pci-x mode transaction termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.13.1. pci 6520 initiator termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.13.1.1. byte count disconnection or satisfaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.13.1.2. pci 6520 master abort termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.13.2. pci 6520 target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.13.2.1. pci 6520 disconnects at next adb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.13.2.2. pci 6520 retry termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.13.2.3. pci 6520 split response termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.14. pci-x mode bus and data transfer width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.15. connecting conventional pci and pci-x interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.15.1. conventional pci requester, pci-x completer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.15.2. pci-x requester, conventional pci completer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 10. address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2. address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.1. i/o address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.1.1. i/o base and limit address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3. memory address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1. memory-mapped i/o base and limit address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3.2. prefetchable memory base and limit address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4. isa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5. vga support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5.1. vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5.2. vga snoop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.6. private device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 11. transaction ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1. conventional pci transaction ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1. transactions governed by ordering rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.2. general ordering guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.3. ordering rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.4. data synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2. pci-x transaction ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.1. relaxed ordering attribute bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.2. split transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 12. error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. address parity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3. attribute parity errors? pci-x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.4. data parity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.4.1. configuration write transactions to configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.4.2. read transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.4.3. posted write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.4.4. delayed write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.4.4.1. conventional pci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.4.4.2. pci-x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4.5. split completion?pci-x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
contents pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary ix 12.5. data parity error reporting summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.6. system error (p_serr#) reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 13. exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1. concurrent locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. acquiring exclusive access across pci 6520. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3. ending exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 14. pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. primary pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3. secondary pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3.1. secondary bus arbitration using internal arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3.2. rotating-priority scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.3.3. fixed-priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.3.4. secondary bus arbitration using external arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.4. arbitration bus parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.4.1. software controlled pci 64-bit extension signals parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 15. gpio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1. gpio interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2. gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.3. gpio serial stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 16. supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1. primary interface command set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2. secondary interface command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 17. bridge behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1. bridge actions for various cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2. abnormal termination (master abort, initiated by bridge master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.3. parity and error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 18. pci flow-through optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2. precautions when using non-optimized pci master devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.3. posted write flow through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.4. delayed read flow through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5. read cycle optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5.1. primary and secondary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5.2. primary and secondary incremental prefetch count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.5.3. primary and secondary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.6. read prefetch boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 19. fifo architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2. memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2.1. pci-to-pci-x memory writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2.2. pci-x-to-pci memory writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2.3. pci-x-to-pci-x memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
contents pci 6520cb data book, version 2.0 x preliminary ? 2004 plx technology, inc. all rights reserved. 19.3. memory reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.3.1. pci-to-pci-x memory reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.3.1.1. prefetched data timeout flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3.1.2. setting the prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.1.2.1. pci read from conventional pci port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.1.2.2. pci read from pci-x port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.2. pci-x-to-pci memory reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.3. pci-x-to-pci-x memory reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 20. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2. power management transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 21. vpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 22. testability/debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1. jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1. ieee 1149.1 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.2. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.3. jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.4. jtag reset input trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 23. electrical specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1. general electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2. pll and clock jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.3. pci/pci-x signal timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 24. mechanical specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1. mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2. physical layout with pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 a. using pci 6520. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1. application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 b. pci-x clock and frequency initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1. bus speed and type detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2. secondary clock outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3. internal clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 c. pci 6520cb and pci 6540cb pin comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 d. general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.1. package ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.2. united states and international representatives, and distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-2 d.3. technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-2 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index-1
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary xi figures 1-1. fastlane pci 6000 bridge series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-2. pci 6520 pci-x-to-pci-x bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3. multiple device expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2-1. pci 6520 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3-1. worst-case power dissipation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 4-1. gpio clock mask implementation on system board example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2. clock mask and load shift timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 6-1. sample memory map of smart prefetch upstream memory, regions 1 through 4 . . . . . . . . . . . . . . . 6-40 7-1. serial eeprom data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 9-1. requester attribute bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9-2. split completion address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9-3. completer attribute bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9-4. split completion message attribute bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 14-1. secondary bus arbiter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 19-1. pci 6520 fifo architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 23-1. pci/pci-x signal timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 24-1. pci 6520 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24-2. pci 6520 physical layout with pinout?topside view (a1?a10 through y1?y10) . . . . . . . . . . . . . . 24-4 24-3. pci 6520 physical layout with pinout?topside view (a11?a20 through y11?y20) . . . . . . . . . . . . 24-5
pci 6520cb data book, version 2.0 xii preliminary ? 2004 plx technology, inc. all rights reserved.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary xiii tables 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison . . . . . . . . . . . . . . . . . . . . . . . . 1-2 3-1. pin type abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2. generic pci bus interface pins that follow pci r2.3 and pci-x r1.0b layout guidelines . . . . . . . . . . . 3-2 3-3. clock pin pull-up/pull-down resistor requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-4. primary pci/pci-x bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-5. secondary pci/pci-x bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-6. clock-related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-7. reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-8. jtag/boundary scan pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-9. serial eeprom pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-10. general purpose i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3-11. miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-12. power, ground, and no connect pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 4-1. gpio shift register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-2. gpio serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-3. pci clock frequency division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-4. m66en and pci-xcap encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-5. pll and clock jitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 5-1. reset input effect on pci 6520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-2. pin states during pwrgd and p_rstin# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 6-1. pci configuration register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-2. extended register map?offset from extended register index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6-3. secondary clock frequency values (pcixssr[8:6]; pci:f2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 7-1. serial eeprom address and corresponding pci 6520 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 8-1. conventional pci transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-2. write transaction forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-3. write transaction disconnect address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8-4. read transaction prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8-5. read prefetch address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8-6. device number to idsel s_ad pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8-7. p_serr# assertion requirements in response to master abort on posted write . . . . . . . . . . . . . . . 8-13 8-8. response to posted write target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8-9. p_serr# assertion requirements in response to posted write parity error . . . . . . . . . . . . . . . . . . 8-14 8-10. response to delayed write target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8-11. p_serr# assertion requirements in response to delayed write . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8-12. response to delayed read target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 8-13. p_serr# assertion requirements in response to delayed read . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 9-1. transaction phase definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-2. byte lane assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9-3. pci-x command encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9-4. requester attribute bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9-5. devsel# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9-6. target initial latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9-7. split completion address bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
tables pci 6520cb data book, version 2.0 xiv preliminary ? 2004 plx technology, inc. all rights reserved. 9-8. completer attribute bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9-9. split completion message bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9-10. pci 6520 error message indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9-11. pci 6520 data phase signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9-12. conventional pci-to-pci-x command translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -21 9-13. pci-x-to-conventional pci command translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -22 11-1. conventional pci transaction ordering summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11-2. pci-x transaction ordering and deadlock-avoidance rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-3. pci-x split transactions?case-by-case discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-6 12-1. primary interface parity error detect ed bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-2. secondary interface parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12-3. primary interface data parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12-4. secondary interface data parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12-5. p_perr# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12-6. s_perr# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12-7. p_serr# or s_serr# for data parity error assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 2 15-1. gpio pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 16-1. primary interface supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16-2. secondary interface supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 17-1. bridge actions for various cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 18-1. reprogramming prefetch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 19-1. prefetched data timeout flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 20-1. states and related actions during power management transitions . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 22-1. pci 6520 jtag idcode value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22-2. jtag instructions (ieee standard 1149.1-1990) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 23-1. maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23-2. functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23-3. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23-4. m66en and pci-xcap encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23-5. pll and clock jitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23-6. 66 mhz pci and 133 mhz pci-x signal timing for figure 23-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 24-1. pci 6520 mechanical dimensions for figure 24-1 symbols (in millimeters) . . . . . . . . . . . . . . . . . . . 24-2 c-1. pci 6520cb versus pci 6540cb pin assignment comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c-1 d-1. available package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d-1
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary xv registers 6-1. (pciidr; pci:00h) pci configuration id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-2. (pcicr; pci:04h) primary pci command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-3. (pcisr; pci:06h) primary pci status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-4. (pcirev; pci:08h) pci revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-5. (pciccr; pci:09h ? 0bh) pci class code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-6. (pciclsr; pci:0ch) pci cache line size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-7. (pciltr; pci:0dh) primary pci bus latency timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-8. (pcihtr; pci:0eh) pci header type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-9. (pcibistr; pci:0fh) pci built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-10. (pcipbno; pci:18h) pci primary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-11. (pcisbno; pci:19h) pci secondary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-12. (pcisubno; pci:1ah) pci subordinate bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 8 6-13. (pcisltr; pci:1bh) secondary pci bus latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 8 6-14. (pciiobar; pci:1ch) i/o base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-15. (pciiolmt; pci:1dh) i/o limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-16. (pcissr; pci:1eh) secondary pci status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6-17. (pcimbar; pci:20h) memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-18. (pcimlmt; pci:22h) memory limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-19. (pcipmbar; pci:24h) prefetchable memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 12 6-20. (pcipmlmt; pci:26h) prefetchable memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6-21. (pcipmbaru32; pci:28h) prefetchable memory base upper 32 bits. . . . . . . . . . . . . . . . . . . . . . . 6-13 6-22. (pcipmlmtu32; pci:2ch) prefetchable memory limit upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-23. (pciiobaru16; pci:30h) i/o base upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-24. (pciiolmtu16; pci:32h) i/o limit upper 16 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-25. (cap_ptr; pci:34h) new capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-26. (pciipr; pci:3dh) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-27. (bcntrl; pci:3eh) bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-28. (ccntrl; pci:40h) chip control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6-29. (dcntrl; pci:41h) diagnostic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6-30. (acntrl; pci:42h) arbiter control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6-31. (pftcr; pci:44h) primary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6-32. (tocntrl; pci:45h) timeout control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6-33. (mscopt; pci:46h) miscellaneous options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6-34. (pitlpcnt; pci:48h) primary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6-35. (sitlpcnt; pci:49h) secondary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -23 6-36. (pincpcnt; pci:4ah) primary incremental prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6-37. (sincpcnt; pci:4bh) secondary incremental prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6-38. (pmaxpcnt; pci:4ch) primary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-39. (smaxpcnt; pci:4dh) secondary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-40. (sftcr; pci:4eh) secondary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 26 6-41. (bufcr; pci:4fh) buffer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6-42. (iacntrl; pci:50h) internal arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6-43. (test; pci:52h) test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6-44. (eepcntrl; pci:54h) serial eeprom control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
registers pci 6520cb data book, version 2.0 xvi preliminary ? 2004 plx technology, inc. all rights reserved. 6-45. (eepaddr; pci:55h) serial eeprom address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -30 6-46. (eepdata; pci:56h) serial eeprom data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6-47. (tmrcntrl; pci:61h) timer control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6-48. (tmrcnt; pci:62h) timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6-49. (pserred; pci:64h) p_serr# event disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -32 6-50. (gpiood[3:0]; pci:65h) gpio[3:0] output data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6-51. (gpiooe[3:0]; pci:66h) gpio[3:0] output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6-52. (gpioid[3:0]; pci:67h) gpio[3:0] input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6-53. (clkcntrl; pci:68h) clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6-54. (pserrsr; pci:6ah) p_serr# status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 6-55. (clkrun; pci:6bh) clock run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6-56. (pvtmbar; pci:6ch) private memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-57. (pvtmlmt; pci:6eh) private memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-58. (pvtmbaru32; pci:70h) private memory base upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-59. (pvtmlmtu32; pci:74h) private memory limit upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-60. (rrc; pci:9ch) read-only register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6-61. (gpiood[7:4]; pci:9dh) gpio[7:4] output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6-62. (gpiooe[7:4]; pci:9eh) gpio[7:4] output enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6-63. (gpioid[7:4]; pci:9fh) gpio[7:4] input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6-64. (extridx; pci:d3h) extended register index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6-65. (extrdata; pci:d4h) extended register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6-66. (spul32bar1; ext:10h) region 1 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . . 6-41 6-67. (spuu32bar1; ext:11h) region 1 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . 6-42 6-68. (spul32bar2; ext:12h) region 2 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . . 6-42 6-69. (spuu32bar2; ext:13h) region 2 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . 6-42 6-70. (spul32bar3; ext:14h) region 3 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . . 6-43 6-71. (spuu32bar3; ext:15h) region 3 upstream lower 32-bit smart prefetch bar . . . . . . . . . . . . . 6-43 6-72. (spubard x ; ext:16h?19h) regions 1?4 upstream smart prefetch bar descriptors . . . . . . . . . 6-43 6-73. (pmcapid; pci:dch) power management capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6-74. (pmnext; pci:ddh) power management next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6-75. (pmc; pci:deh) power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 6-76. (pmcsr; pci:e0h) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6-77. (pmcsr_bse; pci:e2h) pmcsr bridge supports extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6-78. (pmcdata; pci:e3h) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 48 6-79. (pvpdid; pci:e8h) vital product data capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6-80. (pvpd_next; pci:e9h) vital product data next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6-81. (pvpdad; pci:eah) vital product data address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6-82. (pvpdata; pci:ech) vpd data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6-83. (pcixcapid; pci:f0h) pci-x capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6-84. (pcix_next; pci:f1h) pci-x next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -50 6-85. (pcixssr; pci:f2h) pci-x secondary status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6-86. (pcixbsr; pci:f4h) pci-x bridge status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 6-87. (pcixupstr; pci:f8h) pci-x upstream split transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 6-88. (pcixdnstr; pci:fch) pci-x downstream split transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary xvii preface the information contained in this document is subject to change without notice. although an effort has been made maintain accurate information, there may be misleading or even incorrect statements made herein. supplemental documentation the following is a list of documentation to provide further details: pci local bus specification, revision 2.1 , june 1, 1995 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci local bus specification, revision 2.3 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci to pci bridge architecture specification , revision 1.2 , june 9, 2003 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci bus power management interface specification, revision 1.1 , december 18, 1998 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci-x addendum to pci local bus specification, revision 1.0b pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture , 1990 the institute of electrical and electronics engineers, inc. 445 hoes lane, po box 1331, piscataway, nj 08855-1331, usa tel: 800 678-4333 (domestic only) or 732 981-0060, fax: 732 981-1721, http://www.ieee.org/portal/index.jsp
preface pci 6520cb data book, version 2.0 xviii preliminary ? 2004 plx technology, inc. all rights reserved. note: in this data book, shortened titles are provided to the previous ly listed documents. the following table lists these abbreviati ons. data assignment conventions revision history supplemental documentation abbreviations abbreviation document pci r2.1 pci local bus specification, revision 2.1 pci r2.3 pci local bus specification, revision 2.3 p-to-p bridge r1.2 pci to pci bridge architecture specification, revision 1.2 pci power mgmt. r1.1 pci bus power management interface specification , revision 1.1 pci-x r1.0b pci-x addendum to pci local bus specification, revision 1.0b ieee standard 1149.1-1990 ieee standard test access port and boundary-scan architecture data assignment conventions data width pci 6520 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) dword/dword 8 bytes (64 bits) qword/qword date version comments 04/04 1.0 production release, silicon revision bb. 05/04 2.0 production release, silicon revision cb.
transparent pci-x-to-pci-x bridge asynchronous 64-bit, 133 mhz pci-x-to-pci-x bridge for servers, storage, may 2004 telecommunications, networking, and embedded applications version 2.0 and high-performance 10-kb buffer pci-x-to-pci bridging pci 6520 pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary xix feature summary feature summary the plx fastlane? pci 6520 pci-x-to-pci-x bridge is a device capable of 64-bit, 133 mhz operation. the device is designed for high-performance and high-availability uses such as pci-x slot expansion, pci-x-to-pci conversion, multi-device attachment, and frequency conversion. the pci 6520 has sophisticated buffer management and buffer configuration options designed to provide customizable performance for efficient throughput. pci-x r1.0b -compliant at 64-bit, 133 mhz backward compatible with pci r2.3 support for input-pin-enforced pci-x operation 5v tolerant i/o asynchronous design for primary and secondary ports 33 to 133 mhz operation either port may run at the higher frequency 8 gpio pins with output control, with power-up status latch capabilities primary port can be set to pci-x protocol, without requiring the normal reset initialization sequence flow-through, zero wait state bursts of up to 4 kb optimal for large volume data transfer supports up to four simultaneous posted writes and delayed transactions in each direction supports up to four simultaneous split transactions in each direction in pci-x mode optional segmented 1-kb buffer for each of the four read fifo entries 10-kb buffers 1-kb downstream posted write buffer 1-kb upstream posted write buffer 4-kb downstream read data buffer 4-kb upstream read data buffer configurable prefetch size of up to 2 kb ideal for pci-to-pci-x transfers 5 secondary clock outputs pin-controlled enable individual maskable control supports downstream and upstream lock supports secondary port pci/pci-x private devices and private memory space (equivalent to opaque memory) reference clock input option primary and secondary port pci-x frequency detection serial eeprom loadable programmable pci read-only register configurations programmable arbitration for eight secondary bus masters optional external arbiter pci mobile design guide and power management d 3cold wakeup capable enhanced address decoding supports 32-bit i/o address range 32-bit memory-mapped i/o address range isa-aware mode for legacy support in the first 64 kb of i/o address range vga addressing and palette snooping support ieee standard 1149.1-1990 jtag interface low power 0.25 cmos process industry standard 27 x 27 mm 380-pin (ball) pbga package
pci 6520cb data book, version 2.0 xx preliminary ? 2004 plx technology, inc. all rights reserved. feature summary pci 6520 block diagram primary bus secondary bus 4-entry wr i t e buffer (1 kb) 4-entry read buffer (4 kb) 4-entry read buffer (4 kb) 4-entry wr i te buffer (1 kb) gpio serial eeprom clock buffers pci arbiter system detect
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 1-1 1?introduction 1 introduction this section provides information about plx technology, inc., and its products, the fastlane? pci 6000 bridge series, and pci 6520 features and applications. 1.1 company and product information plx technology, inc., is the leading supplier of standard interconnect silicon to the storage, communications, server, and embedded-control industries. plx?s comprehensive i/o interconnect product offering ranges from i/o accelerators, pci-to-pci bridges, pci-x-to-pci-x bridges, and hypertransport? bridges to the plx pci express-based family of switches and bridges currently under development. in addition to a broad product offering, plx provides development tool support through software development kits (sdks), hardware rapid development kits (rdks), and third-party tool support through the plx partner program. our complete tool offering, combined with leadership plx silicon, enables system designers to maximize system throughput, lower development costs, minimize system design risk, and provide faster time to market. the plx commitment to meeting customer requirements extends beyond complete product solutions, and includes active participation in industry associations. plx contributes to the key standard-setting bodies in our industry, including pci-sig? (the special interest group responsible for the creation and release of all pci specifications), picmg ? (the organization responsible for compactpci and the new advancedtca? standard for fabrics), hypertransport? consortium, and blade systems alliance (blades). furthermore, plx is a key developer for pci express technology and a member of the intel developers network for pci express technology. founded in 1986, plx has been developing products based on the pci industry standard since 1994. plx is publicly traded (nasdaq:plxt) and headquartered in sunnyvale, ca, usa, with other domestic offices in utah and southern california. plx european operations are based in the united kingdom and asian operations are based in china and japan. 1.2 fastlane pci 6000 bridge series the plx fastlane pci 6000 series offers the industry?s broadest set of pci-to-pci and pci-x-to-pci-x bridges. these bridges allow additional devices to be attached to the pci bus, and provide the ability to include intelligent adapters on a pci bus. in addition, these bridges allow pci buses of different speeds to be part of the same subsystem. (refer to table 1-1 and figure 1-1.) the plx pci and pci-x family of interconnect products include both pci-to-pci and pci-x-to-pci-x bridging devices, offering system designers innovative features along with improved i/o performance. the plx fastlane pci 6000 series of pci-to-pci bridging products provide support for the entire range of current pci bus data widths and speeds, including 32-bit 33 mhz, 64-bit 66 mhz, and the latest 64-bit 133 mhz pci-x variety of the standard. the fastlane pci 6000 product line is distinguished by featuring the widest range of options, lowest power requirements, highest performance, and smallest footprint in the industry. the product line includes features such as the ability to clock the pci bus segments asynchronously to one another. the entire line of plx bridging products are designed to provide high-performance interconnect for servers, storage, telecommunications, networking, and embedded applications. like all plx interconnect chips, the fastlane pci 6000 series products are supported by plx comprehensive reference design tools and the industry-recognized plx support infrastructure.
section 1 introduction fastlane pci 6000 bridge series pci 6520cb data book, version 2.0 1-2 preliminary ? 2004 plx technology, inc. all rights reserved. table 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison features pci 6140-aa33pc pci 6150-bb66bc pci 6150-bb66pc pci 6152-cc33bc pci 6152-cc33pc pci 6152-cc66bc pci 6156-da33pc pci bus type 32-bit 33 mhz pci 32-bit 66 mhz pci 32-bit 33 mhz pci 32-bit 66 mhz pci 32-bit 33 mhz pci pci local bus support r2.1 compliant r2.3 compliant r2.2 compliant r2.2 compliant r2.2 compliant 3.3 and 5v tolerant i/o yes yes yes yes yes asynchronous operation no 25 to 66 mhz no no no power dissipation 200 mw 1.8w 300 mw 300 mw 300 mw gpio interface no four gpio pins four gpio pins four gpio pins no transparency modes transparent only transparent only transparent only transpar ent only transparent only compactpci- compatible hot swap friendly r2.0 with pi = 1 friendly friendly ? data fifo ? 1 kb fifo ? ? ? number of bus masters on secondary bus up to 4 up to 9 up to 4 up to 4 up to 10 retry architecture standard standard performance- optimized performance- optimized performance- optimized programmable flow-through ?yes??? programmable prefetch not specified up to 4 kb n/a n/a n/a zero wait state burst up to 1 kb up to 1 kb up to 1 kb up to 1 kb up to 1 kb serial eeprom support ? yes yes yes yes vital product data registers ? yes yes yes yes d 3 wakeup power management yes yes yes yes yes secondary clock outputs yes yes yes yes yes jtag support ? ieee 1149.1 compliant ??? packaging pqfp-128 pbga-256 tiny bga-160 tiny bga-160 pqfp-208 pqfp-208 pqfp-160 package size 23 x 17 mm 17 x 17 mm 15 x 15 mm 15 x 15 mm 31 x 31 mm 31 x 31 mm 32 x 32 mm rapid development kit pci 6140rdk pci 6150rdk pci 6152rdk pci 6152rdk pci 6156rdk
section 1 fastlane pci 6000 bridge series introduction pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 1-3 1?introduction features pci 6350-aa66pc pci 6154-bb66bc pci 6254-bb66bc pci 6520-xx pci 6540-xx pci bus type 32-bit 66 mhz pci 64-bit 66 mhz pci 64-bit 66 mhz 64-bit 133 mhz pci-x 64-bit 133 mhz pci-x pci local bus support r2.2 compliant r2.3 compliant r2.3 compliant r2.3 compliant r2.3 compliant 3.3 and 5v tolerant i/o yes yes yes yes yes asynchronous operation yes 25 to 66 mhz 25 to 66 mhz 33 to 133 mhz 25 to 133 mhz power dissipation 1.47w 2.0w 2.0w 1.0w 1.0w gpio interface four gpio pins four gpio pins 16 gpio pins 8 gpio pins 16 gpio pins transparency modes transparent only transparent only transparent, non-transparent and universal modes transparent only transparent, non-transparent and universal modes compactpci- compatible hot swap ? ? r2.0 with pi = 1 ? r2.0 with pi = 1 data fifo 192 byte 1 kb fifo 1 kb fifo 10 kb fifo 10 kb fifo number of bus masters on secondary bus up to 9 up to 9 up to 9 up to 8 up to 8 retry architecture standard standard standard standard standard programmable flow-through yes yes yes yes yes programmable prefetch up to 2 kb up to 4 kb up to 4 kb up to 4 kb up to 4 kb zero wait state burst up to 4 kb up to 1 kb up to 1 kb up to 4 kb up to 4 kb serial eeprom support yes yes yes yes yes vital product data registers yes yes yes yes yes d 3 wakeup power management yes yes yes yes yes secondary clock outputs yes yes yes yes yes jtag support ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant packaging pbga-256 pbga-304 pbga-365 pbga-380 pbga-380 pqfp-208 package size 17 x 17 mm 31 x 31 mm 31 x 31 mm 27 x 27 mm 27 x 27 mm 31 x 31 mm rapid development kit pci 6350rdk pci 6154rdk pci 6254rdk pci 6520rdk pci 6540rdk table 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison (continued)
section 1 introduction fastlane pci 6000 bridge series pci 6520cb data book, version 2.0 1-4 preliminary ? 2004 plx technology, inc. all rights reserved. figure 1-1. fastlane pci 6000 bridge series pci 6140 32-bit 33 mhz pqfp 133 mhz 33 mhz 66 mhz pci 6520 trans pci 6540 non-trans 32-bit 66 mhz pbga pci 6150 32-bit 33/66 mhz tinybga pci 6152 32-bit 66 mhz pqfp pci 6350 pci 6254 64-bit 66 mhz non-trans pci 6154 64-bit 66 mhz trans a s y n c h r o n o u s pci 6156 32-bit 33 mhz for dvr 10 masters
section 1 feature description introduction pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 1-5 1?introduction 1.2.1 pci 6520 as illustrated in figure 1-2, the pci 6520 is a two-port device providing full asynchronous operation between the primary and secondary ports. the secondary bus may be run faster than the primary bus, and vice versa. pci-x is the next generation of the industry-standard pci bus. this standard provides complete backward compatibility in terms of electrical characteristics, software, and form factor, and when used in pci-x mode, the maximum transfer speed increases to 133 mhz, allowing a maximum bursting bandwidth of 1 gbps. alternatively, pci-x allows greater electrical expansion of the pci bus at 66 mhz by registering data transfers. a transparent pci bridge is meant to provide electrical isolation to the system. it allows additional loads (and devices) to be attached to the bus, and can also be used to operate dissimilar pci bus data widths and speeds on the same system. for example , a transparent bridge can allow several 64-bit, 66 mhz pci devices to attach to a 133 mhz pci-x slot. an asynchronous bridge provides the ability to run each port from a completely independent clock. this allows the system designer to provide the highest performance on each side of the bridge, without forcing one side to slow down based on a slower device on the other side of the bridge. the advantage of an asynchronous bridge is that the two clock domains can be arbitrarily different, and not based on a synchronous version of the other clock. figure 1-2. pci 6520 pci-x-to-pci-x bridge 1.3 feature description the pci 6520 provides a range of added-value features to system designers, including: two pci-x ports, each capable of running at the full 64-bit, 133 mhz speed backward compatible to pci r2.3 asynchronous primary and secondary ports ports can operate from 33 mhz to 133 mhz either port can operate slower or faster than the other port 5v tolerant i/o programmable prefetch programmable flow through zero wait state burst 10-kb data fifo 5 secondary clock outputs reference clock input for frequency detection pci power management support arbitration support for eight secondary bus masters serial eeprom for configuration 16 general purpose i/o pins vital product data (vpd) jtag boundary scan pci 6520 asynchronous transparent power management 8 bus master support 8 gpios serial eeprom support 5 external clock buffers secondary pci-x bus primary pci-x bus
section 1 introduction applications pci 6520cb data book, version 2.0 1-6 preliminary ? 2004 plx technology, inc. all rights reserved. 1.4 applications 1.4.1 multiple device expansion figure 1-3 illustrates the pci 6520 being used to provide electrical isolation to the pci-x bus. this is necessary because pci-x slots restrict the number of loads that can be accommodated. the devices on the secondary port can be pci or pci-x , and the bus can operate at a range of frequencies and bus data widths. this configuration is a common mechanism for providing multiple, high-speed ethernet or fibre channel connections on a single pci-x card. figure 1-3. multiple device expansion pci-x bus pci 6520 pci or pci-x device pci or pci-x device pci or pci-x device pci or pci-x device primary port secondary port
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 2-1 2?functional overview 2 functional overview this section describes general operation of the pci 6520 bridge, and provides an overview of write and read transactions. 2.1 general operation as illustrated in figure 2-1, the pci 6520 uses programmable buffers to regulate data flow between the primary and secondary ports. there are two sets of buffers?one for downstream commands (data flows from primary-to-secondary bus) and one for upstream commands (data flows from secondary-to- primary bus). the buffers are organized as follows: 4-entry write buffer (1 kb) 4-entry read buffer (4 kb) each pci and/or pci-x port can run at different (asynchronous) frequencies, which allows the designer to optimize the performance of each bus. both the primary and secondary pci and/or pci-x ports may be operated at 32- or 64-bit bus data widths, and the two buses may be of different widths. the pci 6520 provides an internal arbiter function on the secondary bus, for up to eight secondary bus masters. however, the internal arbiter may be disabled if an external arbiter is used. the pci 6520 also sources five secondary pci and/or pci-x clock outputs. the pci 6520 provides features satisfying the requirements of pci power mgmt. r1.1 , supporting power management states d 0 through d 3cold and d 3hot . (refer to section 20, ?power management,? for further details.) the pci 6520 supports a serial eeprom device for register configuration data. this allows the pci 6520 to automatically load custom configuration upon power-up, which minimizes the software overhead of configuring the bridge through a host processor. the pci 6520 fully supports vital product data (vpd) by providing the address, data, and control registers (pvpdad; pci:eah, pvpdata; pci:ech, pvpdid; pci:e8h, and pvpd_next; pci:e9h) for accessing vpd stored in the unused portion of the serial eeprom. vpd allows reading or writing of user data to the upper 192 bytes of serial eeprom space, and that data can contain information such as board serial number, software revision, firmware revision, or other data required for non-volatile storage. (refer to section 21, ?vpd,? for further details.) figure 2-1. pci 6520 block diagram primary bus secondary bus 4-entry wr i t e buffer (1 kb) 4-entry read buffer (4 kb) 4-entry read buffer (4 kb) 4-entry wr i te buffer (1 kb) gpio serial eeprom clock buffers pci arbiter system detect
section 2 functional overview write transactions pci 6520cb data book, version 2.0 2-2 preliminary ? 2004 plx technology, inc. all rights reserved. 2.2 write transactions the primary or secondary bus accomplishes a write operation by placing the address and data into the write buffer . this initiates a pci write operation on the other bus. the write operation is called a posted write operation, because the initiating bus performs the write, then moves on without waiting for the operation to complete. the pci 6520 provides the ability to combine write operations when the operations are directed at the same address range. the device recognizes when write operations are directed at consecutive addresses, and accumulates and bursts those write operations to the pci bus for increased bandwidth. in addition, the pci 6520 has the capability to start a write operation before receiving all write data. in this case, the write operation begins when there is sufficient write data to begin the burst, providing a flow-through operation as the balance of the write data arrives in the device. 2.3 read transactions when the downstream or upstream bus needs to read data from the other bus, the bus places the read request into the read command queue . this initiates a read operation on the other bus, and the data is placed into the associated read buffer as it returns. for pci-x transactions, the pci 6520 also prefetches data as defined in the original read operation. for pci transactions, there is an additional prefetch mechanism when returning the requested read data. in this mode, the pci 6520 can be programmed to prefetch up to 2 kb of data at a time. this data is stored in the read buffer and is not flushed until the buffer times out. if requested, prefetched data can be delivered to the pci bus without the normal read on the other bus.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-1 3?pin description 3 pin description this section describes the pci 6520 pins (balls), including pin summary, pull-up and pull-down resistor recommendations, power supply de-coupling, and pinout listings. 3.1 pin summary tables 3-4 through table 3-12 describe each pci 6520 pin: pci-x primary bus interface pci-x secondary bus interface clock-related reset jtag serial eeprom interface gpio miscellaneous power, ground, and no connect for a visual view of the pci 6520 pinout, refer to section 24, ?mechanical specs.? table 3-1 lists abbreviations used in section 3 to represent various pin types. table 3-1. pin type abbreviations abbreviation pin type i cmos input (5v input tolerant, i/o v dd =3.3v) i/o cmos bi-directional input output (5v input tolerant, i/o v dd =3.3v) o cmos output od open drain oz output three-state pci pci/pci-x compliant pi pci-x input (5v input tolerant, i/o v dd =3.3v) po pci-x output pu signal is internally pulled up psts pci-x sustained three-state output, drive high for one clk before floating (5v input tolerant, i/o v dd =3.3v) pts pci-x three-state bi-directional (5v input tolerant, i/o v dd =3.3v)
section 3 pin description pull-up and pull-down resistor recommendations pci 6520cb data book, version 2.0 3-2 preliminary ? 2004 plx technology, inc. all rights reserved. 3.2 pull-up and pull-down resistor recommendations pull-up and pull-down resistor values are not critical. with the exception of those mentioned in section 3.2.1, a 10k-ohm resistor is recommended unless stated otherwise. 3.2.1 pci bus interface pins the pins detailed in table 3-2 are generic primary and secondary pci interface pins. when producing motherboards, system slot cards, adapter cards, backplanes, and so forth, the termination of these pins should follow the guidelines detailed in pci r2.3 and pci-x r1.0b . the following guidelines are not exhaustive and should be read in conjunction with the appropriate sections of pci r2.3 and pci-x r1.0b . pci control signals require a pull-up resistor on the motherboard to ensure that these signals are always at valid values when a pci bus agent is not driving the bus. these control signals include ack64#, devsel#, frame#, irdy#, lock#, perr#, req64#, serr#, stop#, and trdy#. the 32-bit point-to-point and shared bus signals do not require pull-up resistors, as bus parking ensures that these signals remain stable. the other 64-bit signals? ad[63:32], cbe[7:4]# and par64?also require pull-up resistors, as these signals are not driven during 32-bit transactions. depending on the application, m66en may also require a pull-up resistor. the value of these pull-up resistors depends on the bus loading. pci r2.3 provides formulas for calculating these resistors. when making adapter cards in which the pci 6520 primary port is wired to the pci connector, pull-up resistors are not required because they are pre-installed on the motherboard. based on the above, in an embedded design, pull-up resistors may be required for pci control signals on the primary and secondary buses. whereas, for a pci adapter card design, pull-up resistors are required only on the pci 6520 port that is not connected to the motherboard or host system. s_req[7:1]# inputs must be pulled high with a 10k-ohm pull-up resistor. s_req0# also requires a 10k-ohm pull-up resistor if s_cfn#=0. table 3-2. generic pci bus interface pins that follow pci r2.3 and pci-x r1.0b layout guidelines bus pin name primary p_ack64#, p_ad[63:0], p_cbe[7:0]#, p_devsel#, p_frame#, p_gnt#, p_idsel, p_irdy#. p_lock#, p_m66en, p_par, p_par64, p_perr#, p_req#, p_req64#, p_serr#, p_stop#, p_trdy# secondary s_ack64#, s_ad[63:0], s_cbe[7:0]#, s_devsel#, s_frame#, s_gnt[7:0]#, s_irdy#. s_lock#, s_m66en, s_par, s_par64, s_perr#, s_req[7:0]#, s_req64#, s_serr#, s_stop#, s_trdy#
section 3 pull-up and pull-down resistor recommendations pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-3 3?pin description 3.2.2 clock-related pins clock routing is detailed in section 4, ?clocking.? pull-up resistors are not required on the s_clko[4:0] pins; however, a series termination resistor is required when using these pins. s_clko0 may require a pull-up resistor when this pin is used as a result of s_clkoff=1, or disabled (clkcntrl [1:0]=11b; pci:68h). s_clko[4:0] may also require pull-up resistors if they are disabled by pulling msk_in high. table 3-3 delineates the remaining clock pin resistor requirements. notes: * refer to section 4.6, ?pll and clock jitter,? for further details regarding p_pllen# and s_pllen# when used in low frequency applications. ** refer also to the text preceding this table. 3.2.3 reset pins the p_rstin# reset signal may require a pull-up resistor, depending on the application. the s_rstout# reset signal does not require a pull-up nor pull-down resistor. the pwrgd signal should be pulled to 3.3v or driven high when the 3.3v supply is stable. it should not be connected to 5v. note: pwrgd requires a clean, low-to-high transition. the pwrgd input is not internally de-bounced; therefore, this input must be pulled up to 3.3v, rather than 5v. 3.2.4 jtag/boundary scan pins the tck, tdi, and tms jtag signals must be externally pulled high or low to a known state. the tdo signal must be externally pulled high. the trst# signal must be pulled low, using a 330-ohm resistor. 3.2.5 serial eeprom pins eepclk does not require a pull-up nor pull-down resistor. eepdata requires an external pull-up resistor. 3.2.6 gpio pins when programmed as outputs, the gpio[7:0] pins do not require external pull-up nor pull-down resistors. if configured as inputs, pull the gpio[7:0] pins high or low, depending on the application. 3.2.7 miscellaneous pins the bpcc_en, dev64#, and prv_dev signals may optionally be pulled high or low. s_cfn# may also optionally be pulled high or low, but must be tied low to use the internal arbiter. p_xcap is normally configured by the host. in an embedded system, the p_xcap pin may be pulled high or low. when p_xcap is pulled high, the primary port is forced to use pci-x bus protocol. in general, pull the p_xcap pin low. when p_xcap is pulled low, the primary port bus protocol is set by the pci-x initialization pattern when p_rstin# is de-asserted. tie s_xcap_pu to s_xcap_in by way of a 1k-ohm resistor. s_xcap_in should follow the programmable pull-up and binary input buffer method, as defined in pci-x r1.0b, ?detection of pci-x add-in card capability? appendix. pci-x r1.0b allows detection of conventional pci, pci-x 66 mhz, pci-x 100 mhz (with pcix100mhz=1), or pci-x 133 mhz (with pcix100mhz=0) adapter cards or devices on the secondary interface. p_tst1 and s_tst1 should be pulled high and p_tst0 and s_tst0 should be pulled low. table 3-3. clock pin pull-up/pull-down resistor requirements resistor requirements pin name must pull low p_clkoe, p_cr, s_cr, p_pllen#* pull or tie low or high, or connect to 3.3v power supply s_clkin_stb, s_pllen#* pull high or low if unused oscin, refclk optionally pull high or low msk_in, oscsel#, s_clkoff pull-up or pull-down resistor not required p_clkin, s_clkin, s_clko[4:1]**
section 3 pin description pull-up and pull-down resistor recommendations pci 6520cb data book, version 2.0 3-4 preliminary ? 2004 plx technology, inc. all rights reserved. 3.2.8 system voltage pins for designs and add-in cards that have an independent v io voltage source, and for which proper power sequencing cannot be guaranteed, the current between the v io voltage source and pci 6520 v io pins must be limited to protect the device from long-term undue stress resulting in damage ( such as from resistor insertion). note: by their nature, add-in cards cannot assume proper power sequencing and requirements must be met by system power supplies. use the following guidelines to determine the required resistance value for the p_v io and s_v io pins: 3.3v signaling environments ?40 to 200-ohm resistance between the v io voltage source and the pci 6520 v io pins is recommended if v io is a maximum of 3.6v 3.3 or 5v signaling environments ?40 to 70-ohm resistance is recommended a single resistor can be used if the v io pins are bused, or multiple parallel resistors can be used between the v io voltage source and v io pins. the resistor power dissipation rating depends upon the resistance size and signaling environment. for example, if a single 50-ohm resistor is used in a 5v signaling environment, the worst-case power dissipation would result in 480 mw. (refer to figure 3-1.) if four, 200-ohm resistors are used in parallel, each would be required to dissipate 120 mw. any resistance value within the recommended ranges prevents the device from being damaged, while providing sufficient clamping action to keep the input voltage (v in ) below its maximum rating. a resistance value at the lower end of the range is recommended to provide preferable clamping action, and a sufficient v in margin. 480 mw = (v v) / r (5.5v (maximum signal amplitude, plus 10%) ? 0.6v (1 diode drop)) 2 50 ohms figure 3-1. worst-case power dissipation example
section 3 power supply de-coupling pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-5 3?pin description 3.3 power supply de-coupling de-couple all v dd_core , v dd_io , p_av dd , p_v io , s_av dd , and s_v io lines. the de-coupling level depends on power plane routing and the acceptable power supply noise level. in an ideal case, de-couple all previously listed power supply pins, using a parallel combination of 10 and 100 nf capacitors. use of the 10 nf capacitors is due to the relatively high inductance of 100 nf capacitors, which can prevent the capture of fast transients. due to routing constraints, it may not be possible to add the parallel combination to all supply pins. in this case, the 10 and 100 nf capacitors can be used alternately among the supply pins. low-inductance 100 nf capacitors are available, which may be used in place of the 10 nf/100 nf parallel combination. take care when choosing the capacitor material. some types have poor thermal characteristics, resulting in substantial drops in the capacitance value at higher temperatures. connect de-coupling capacitors to the appropriate ground plane. do not de-couple digital supplies to the clean analog phase-locked loop (pll) grounds or vice versa. phase-locked loops are sensitive to power and ground noise. using the same supply/ground for more than one pll, or the digital supply/ground (core or i/o ring) for either pll is not recommended, as noise coupling into the pll supply/ground can cause pll malfunction. each pll requires a dedicated and independent power supply and ground. ideally, de-couple each pll supply with 100 pf, 47 nf, and 10 f capacitors, in parallel. one set of capacitors is required for each pll supply. in addition to the above, a 10 f bulk de-coupling capacitor for the digital supply is also recommended. the number and placement of this capacitor depends on the power supply and board design.
section 3 pin description pinout pci 6520cb data book, version 2.0 3-6 preliminary ? 2004 plx technology, inc. all rights reserved. 3.4 pinout note: refer to section 3.2 for pull-up and pull-down resistor recommendations not specifically stated in these tables. table 3-4. primary pci/pci-x bus interface pins symbol signal name total pins pin type pin number function p_ack64# primary 64-bit transfer acknowledge 1 i/o psts pci w14 when asserted by the target device, indicates that the target can perform 64-bit data transfers. uses the same timing as p_devsel#. when de-asserting, driven high for one cycle before being placed into a high-impedance state. p_ad[31:0] primary address and data, lower 32 bits 32 i/o pts pci r4, r2, r1, t4, t3, t2, t1, u4, u1, v2, v1, w2, w1, v7, w7, y7, w10, y10, t11, u11, v11, w11, y11, t12, w12, y12, u13, v13, w13, y13, u14, v14 multiplexed address and data bus. provides the lower 32 address and/or data pins. address is indicated by p_frame# assertion during pci and/or pci-x transactions. write data is stable and valid when p_irdy# is asserted and read data is stable and valid when p_trdy# is asserted. data is transferred on rising clock edges when p_irdy# and p_trdy# are asserted. during bus idle, driven by the pci 6520 to valid logic levels when p_gnt# is asserted. additionally, these lines provide a portion of the attribute during the attribute phase of pci-x transactions. (refer to section 14, ?pci bus arbitration,? for further details.) p_ad[63:32] primary address and data, upper 32 bits 32 i/o pts pci v16, w16, y16, u17, v17, w17, y17, y18, w18, u18, y19, w19, v19, w20, v20, u19, u20, t17, t18, t19, t20, r17, r19, r20, p17, p18, p19, p20, n17, n18, n19, n20 multiplexed address and data bus. provides the upper 32 address and/or data pins. during an address phase (when using the dac command and p_req64# is asserted), the upper 32 bits of a 64-bit address are transferred; otherwise, these bits are undefined. during a data phase, the upper 32 bits of data are transferred if a 64-bit transaction is negotiated by p_req64# and p_ack64# assertion. p_cbe[3:0]# primary lower command and byte enables 4 i/o pts pci u3, u8, v10, u12 multiplexed command and byte enable fields. provides the transaction type during the pci and/or pci-x address phase. in the data phase of pci and/or pci-x memory write transactions, p_cbe[3:0]# provide byte enables. during the pci-x attribute phase, these signals provide a portion of the attribute information. during bus idle, the pci 6520 drives p_cbe[3:0]# to valid logic levels when p_gnt# is asserted.
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-7 3?pin description p_cbe[7:4]# primary upper command and byte enables 4 i/o pts pci u15, w15, y15, u16 multiplexed command and byte enable fields. during an address phase (when using the dac command and p_req64# is asserted), the bus command is transferred on these pins; otherwise, p_cbe[7:4]# are reserved and indeterminate. if a 64-bit transaction is negotiated by p_req64# and p_ack64# assertion, then during a pci and/or pci-x memory write transaction data phase, these pins indicate which byte lanes carry meaningful data. p_devsel# primary device select 1 i/o psts pci t9 asserted by the target, indicating that the device is accepting the transaction. as a master, the pci 6520 waits for p_devsel# assertion within five cycles of p_frame# assertion; otherwise, the transaction terminates with a master abort. before being placed into a high-impedance state, p_devsel# is driven to a high state for one cycle. p_frame# primary frame 1 i/o psts pci v8 driven by the initiator of a transaction to indicate the beginning and duration of an access. p_frame# de-assertion indicates the final data phase requested by the initiator. before being placed into a high-impedance state, p_frame# is driven to a high state for one cycle. p_gnt# primary grant 1 pi p4 when asserted, the pci 6520 can access the primary bus. during bus idle with p_gnt# asserted, the pci 6520 drives p_ad x , p_cbe x #, p_par, and p_par64 to valid logic levels. p_idsel primary initialization device select 1pi u2 used as a chip select line for configuration accesses to pci 6520 configuration space and configuration spaces behind the pci 6520 bridge. p_irdy# primary initiator ready 1 i/o psts pci w8 driven by the initiator of a transaction to indicate its ability to complete the current data phase on the primary bus. before being placed into a high-impedance state, p_irdy# is driven to a de-asserted state for one cycle. p_lock# primary lock 1 i/o psts pci w9 asserted by the bus master, indicating an atomic operation that may require multiple transactions to complete. table 3-4. primary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-8 preliminary ? 2004 plx technology, inc. all rights reserved. p_m66en primary 66 mhz enable 1pi m20 set high to allow 66 mhz primary bus operation. along with s_m66en, controls the frequency output to the s_clko[4:0] pins. (refer to section 4, ?clocking,? for further details.) also used with the pci-x initialization pattern to automatically enable and disable the primary pll. p_par primary parity, lower 32 bits 1 i/o pts pci u10 parity is even across p_ad[31:0], p_cbe[3:0]#, and p_par [ such as , an even number of ones (1)]. p_par is an input and valid and stable for one cycle after the address phase (indicated by p_frame# assertion) for address parity. during write transactions, p_par is an output and valid for one clock after p_trdy# assertion. p_par is placed into a high-impedance state one cycle after the p_ad[31:0] lines are placed into a high-impedance state. during bus idle, the pci 6520 drives p_par to a valid logic level when p_gnt# is asserted. during read transactions, p_par is an input and valid for one clock after p_irdy# assertion. p_par64 primary parity, upper 32 bits 1 i/o pts pci m16 parity is even across p_ad[63:32] and p_cbe[7:4]#. p_par64 must be valid for one clock after each address phase on transactions in which p_req64# is asserted. for data phases, after p_par64 is valid, p_par64 remains valid until one clock cycle after the current data phase completes. p_perr# primary parity error 1 i/o psts pci y9 asserted when a data parity error is detected for data received on the primary interface. before being placed into a high-impedance state, p_perr# is driven to a de-asserted state for one cycle. p_req# primary request 1oz p1 asserted by the pci 6520 to request ownership of the primary bus to perform a transaction. the pci 6520 de-asserts p_req# for at least two pci clock cycles before re-asserting it. (refer to section 14.2, ?primary pci bus arbitration,? for further details.) table 3-4. primary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-9 3?pin description p_req64# primary 64-bit transfer request 1 i/o psts pci y14 must be asserted low by the central resource (bus support functions supplied by the host system) during reset to indicate the primary bus is a 64-bit bus. asserted with p_frame# by a pci bus master to request a 64-bit data transfer. the pci 6520 ignores this input during reset. the pci 6520 asserts p_req64# when the secondary pci master performs a 64-bit transfer or the force64 option is enabled (mscopt[15 and/or 11]=1; pci:46h). notes: if p_req64# is high during reset, the primary bus is a 32-bit bus, and the pci 6520 must park the p_ad[63:32], p_cbe[7:4]#, and p_par64 signals. if there is no central resource in the bus to assert p_req64# low during reset, the pci 6520 performs a 32-bit only data transfer and ignores p_req64# on the bus. a three-state buffer with input pin to ground, three-state select pin to bus reset and output pin to p_req64# can assert p_req64# during reset. p_serr# primary system error 1 od t10 p_serr# can be driven low by any device to indicate a system error condition. the pci 6520 drives p_serr# if one of the following conditions is met: address parity error posted write data parity error on target bus s_serr# is asserted master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout p_stop# primary stop 1 i/o psts pci u9 asserted by the target to end the transaction on the current data phase. before being placed into a high-impedance state, p_stop# is driven to a de-asserted state for one cycle. table 3-4. primary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-10 preliminary ? 2004 plx technology, inc. all rights reserved. p_trdy# primary target ready 1 i/o psts pci y8 driven by the target of a transaction to indicate its ability to complete the current data phase on the primary bus. before being placed into a high-impedance state, p_trdy# is driven to a de-asserted state for one cycle. total 88 table 3-5. secondary pci/pci-x bus interface pins symbol signal name total pins pin type pin number function s_ack64# secondary 64-bit transfer acknowledge 1 i/o psts pci b17 when asserted by the target device, indicates that the target can perform 64-bit data transfers. uses the same timing as s_devsel#. when de-asserting, driven high for one cycle before being placed into a high-impedance state. s_ad[31:0] secondary address and data, lower 32 bits 32 i/o pts pci a6, b6, c6, d6, a7, b7, c7, d7, c8, d8, a9, b9, d9, e9, a10, b10, e12, a13, b13, c13, d13, a14, b14, c14, a15, b15, d15, a16, b16, c16, d16, a17 multiplexed address and data bus. provides the lower 32 address and/or data pins. address is indicated by s_frame# assertion during pci and/or pci-x transactions. write data is stable and valid when s_irdy# is asserted and read data is stable and valid when s_trdy# is asserted. data is transferred on rising clock edges when s_irdy# and s_trdy# are asserted. driven to a low logic level (0) when s_rstout# is asserted. during bus idle, driven by the pci 6520 to valid logic levels when the pci 6520 is granted secondary bus ownership. additionally, these lines provide a portion of the attribute during the attribute phase of pci-x transactions. (refer to section 14, ?pci bus arbitration,? for further details.) s_ad[63:32] secondary address and data, upper 32 bits 32 i/o pts pci b20, c20, c19, d20, d19, d18, d17, e20, e19, e18, e17, f20, f19, f17, g20, g19, g18, g17, h20, h19, h18, h17, j20, j19, j17, j16, k20, k19, k18, k17, k16, l20 multiplexed address and data bus. provides the upper 32 address and/or data pins. during an address phase (when using the dac command and s_req64# is asserted), the upper 32 bits of a 64-bit address are transferred; otherwise, these bits are undefined. during a data phase, the upper 32 bits of data are transferred if a 64-bit transaction is negotiated by s_req64# and s_ack64# assertion. driven to a low logic level (0) when s_rstout# is asserted. table 3-4. primary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-11 3?pin description s_cbe[3:0]# secondary lower command and byte enables 4 i/o pts pci b8, c10, d12, d14 multiplexed command and byte enable fields. provides the transaction type during the pci and/or pci-x address phase. in the data phase of pci and/or pci-x memory write transactions, s_cbe[3:0]# provide the byte enables. during the pci-x attribute phase, these signals provide a portion of the attribute information. driven to a low logic level (0) when s_rstout# is asserted. during bus idle, the pci 6520 drives s_cbe[3:0]# to valid logic levels when the pci 6520 is granted secondary bus ownership. (refer to section 14, ?pci bus arbitration,? for further details.) s_cbe[7:4]# secondary upper command and byte enables 4 i/o pts pci a18, b18, a19, b19 multiplexed command and byte enable fields. during an address phase (when using the dac command and s_req64# is asserted), the bus command is transferred on these pins; otherwise, s_cbe[7:4]# are reserved and indeterminate. if a 64-bit transaction is negotiated by s_req64# and s_ack64# assertion, then during a pci and/or pci-x memory write transaction data phase, these pins indicate which byte lanes carry meaningful data. driven to a low logic level (0) when s_rstout# is asserted. s_devsel# secondary device select 1 i/o psts pci b11 asserted by the target, indicating that the device is accepting the transaction. as a master, the pci 6520 waits for the s_devsel# assertion within five cycles of s_frame# assertion; otherwise, the transaction terminates with a master abort. before being placed into a high-impedance state, s_devsel# is driven to a high state for one cycle. s_frame# secondary frame 1 i/o psts pci d10 driven by the initiator of a transaction to indicate the beginning and duration of an access. s_frame# de-assertion indicates the final data phase requested by the initiator. before being placed into a high-impedance state, s_frame# is driven to a high state for one cycle. s_gnt0# secondary grant 0 1 if s_cfn#=0 oz otherwise pi e1 asserted by the pci 6520 to grant the secondary bus to a secondary bus master when using internal arbitration (s_cfn#=0). when external arbitration is active (s_cfn#=1), s_gnt0# becomes the external bus grant input to the pci 6520. during bus idle with s_gnt0# asserted, the pci 6520 drives s_ad x , s_cbe x #, s_par, and s_par64 to valid logic levels. table 3-5. secondary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-12 preliminary ? 2004 plx technology, inc. all rights reserved. s_gnt[7:1]# secondary internal arbiter grant 7 to 1 7 if s_cfn#=0 oz otherwise pi g2, g3, g4, f1, f2, f3, f4 asserted by the pci 6520 to grant the secondary bus to a secondary bus master. the pci 6520 de-asserts s_gnt[7:1]# for at least two pci clock cycles before re-asserting them. pull s_gnt[7:1]# high if s_cfn#=1. s_irdy# secondary initiator ready 1 i/o psts pci e10 driven by the initiator of a transaction to indicate its ability to complete the current data phase on the secondary bus. before being placed into a high-impedance state, s_irdy# is driven to a de-asserted state for one cycle. s_lock# secondary lock 1 i/o psts pci d11 asserted by the bus master, indicating an atomic operation that may require multiple transactions to complete. s_m66en secondary 66 mhz enable 1 if p_m66en=0 od otherwise pi l16 driven low if p_m66en is low; otherwise, driven from outside to select 66 or 33 mhz. s_m66en must be pulled high with a 10k-ohm resistor. along with p_m66en, controls the frequency output to the s_clko[4:0] pins. (refer to section 4, ?clocking,? for further details.) s_par secondary parity, lower 32 bits 1 i/o pts pci b12 parity is even across s_ad[31:0], s_cbe[3:0]#, and s_par [ such as , an even number of ones (1)]. s_par is an input and valid and stable one cycle after the address phase (indicated by s_frame# assertion) for address parity. during write transactions, s_par is an output and valid for one clock after s_trdy# assertion. s_par is placed into a high-impedance state one cycle after the s_ad[31:0] lines are placed into a high-impedance state. driven to a low logic level (0) when s_rstout# is asserted. during bus idle, the pci 6520 drives s_par to a valid logic level when the pci 6520 is granted secondary bus ownership. (refer to section 14, ?pci bus arbitration,? for further details.) during read transactions, s_par is an input and valid for one clock after s_irdy# assertion. table 3-5. secondary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-13 3?pin description s_par64 secondary parity, upper 32 bits 1 i/o pts pci l19 parity is even across s_ad[63:32] and s_cbe[7:4]#. s_par64 must be valid for one clock after each address phase on transactions in which s_req64# is asserted. for data phases, after s_par64 is valid, s_par64 remains valid until one clock cycle after the current data phase completes. driven to a low logic level (0) when s_rstout# is asserted. s_perr# secondary parity error 1 i/o psts pci e11 asserted when a data parity error is detected for data received on the secondary interface. before being placed into a high-impedance state, s_perr# is driven to a de-asserted state for one cycle. s_req0# secondary request 0 1 if s_cfn#=0 pi otherwise oz b1 when the internal pci arbiter is enabled (s_cfn#=0), s_req0# is asserted by an external device to request secondary bus ownership to perform a transaction. when using external arbitration (s_cfn#=1), s_req0# becomes the external request output from the pci 6520. if s_cfn#=0, s_req0# must be externally pulled up through a 10k-ohm resistor. (refer to section 14.3.4, ?secondary bus arbitration using external arbiter,? for further details.) s_req[7:1]# secondary internal arbiter request 7 to 1 7pi e3, e4, d1, d2, d3, c1, c2 asserted by an external device to request secondary bus ownership to perform a transaction. s_req[7:1]# must be externally pulled up through 10k-ohm resistors, including those pins which are not c onnected to other bus master devices. s_req[7:1]# are not used when s_cfn#=1. table 3-5. secondary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-14 preliminary ? 2004 plx technology, inc. all rights reserved. s_req64# secondary 64-bit transfer request 1 i/o psts pci c17 must be asserted low by the central resource (bus support functions supplied by the host system) during reset to indicate the primary bus is a 64-bit bus. asserted with s_frame# by a secondary pci bus master to request a 64-bit data transfer. the pci 6520 asserts s_req64# low during reset and when the primary pci master performs a 64-bit transfer or the force64 option is enabled (mscopt[15 and/or 11]=1; pci:46h). notes: if s_req64# is high during reset, the primary bus is a 32-bit bus, and the pci 6520 must park the s_ad[63:32], s_cbe[7:4]#, and s_par64 signals. if there is no central resource in the bus to assert s_req64# low during reset, the pci 6520 performs a 32-bit only data transfer and ignores s_req64# on the bus. a three- state buffer with input pin to ground, three- state select pin to bus reset and output pin to s_req64# can assert s_req64# during reset. s_serr# secondary system error 1pi a12 s_serr# can be driven low by any device to indicate a system error condition. s_stop# secondary stop 1 i/o psts pci c11 asserted by the secondary target to end the transaction on the current data phase. before being placed into a high-impedance state, s_stop# is driven to a de-asserted state for one cycle. s_trdy# secondary target ready 1 i/o psts pci a11 driven by the target of a transaction to indicate its ability to complete the current data phase on the secondary bus. before being placed into a high-impedance state, s_trdy# is driven to a de-asserted state for one cycle. total 101 table 3-5. secondary pci/pci-x bus interface pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-15 3?pin description table 3-6. clock-related pins symbol signal name total pins pin type pin number function msk_in mask 1 pi j1 used with gpio[2, 0] to shift in a serial stream of bits to the clock control register (clkcntrl; pci:68h) to enable or disable the s_clko[4:0] clock output buffers during reset. msk_in can be pulled low to enable, or high to disable, all s_clko[4:0] buffers. notes: refer to section 4.2.2, ?secondary clock control,? for further details. s_clkoff can also be used to enable or disable s_clko[4:0]. oscin external oscillator input 1pi p3 external clock input used to generate secondary output clocks when enabled through the oscsel# pin. pull high or low if unused. oscsel# external oscillator enable 1pi n1 enables external clock connection for the secondary interface. if low, the secondary bus clock outputs use the clock signal from oscin, instead of p_clkin, to generate s_clko[4:0]. may optionally be pulled high or low. p_clkin primary pci clock input 1 pi n4 provides timing for primary interface transactions. p_clkoe primary clock output enable 1pi r5 test pin. must be pulled low for normal operation. values: 0 = disables test function. 1 = s_clko3 is for primary pll test and s_clko4 is for secondary pll test. p_cr primary pll range control 1pi t6 selects the primary pll operating range. must be pulled low for normal operation. pull or tie to v ss . p_pllen# primary pll enable 1pi t7 values: 0 = enables primary pll. 1 = disables primary pll. must be pulled low. notes: the pci-x initialization pattern and p_m66en may also be used to automatically enable the primary pll. refer to section 4.6, ?pll and clock jitter,? for further details regarding use in low frequency applications. refclk reference clock input 1pi p2 when used, refclk should be a fixed frequency input (14.318 mhz recommended), which is used by the internal counters to determine the primary and secondary pci clock frequency. pull high or low if unused.
section 3 pin description pinout pci 6520cb data book, version 2.0 3-16 preliminary ? 2004 plx technology, inc. all rights reserved. s_clkin secondary pci clock input 1pi j5 provides timing for all secondary interface transactions. s_clkin_stb secondary clock input stable 1pi k5 values: 0 = s_rstout# remains asserted until s_clkin_stb is 1. 1 = indicates external secondary clock pll and external s_clkin are stable. pull or tie low or high, or connect to a 3.3v power supply. if not used, connect to a 3.3v power supply. s_clko0 secondary clock 0 1 if s_clkoff=0 po otherwise pi k3 s_clko0 is used as a clock output buffer, which is derived from the p_clkin or oscin (if oscsel# is low) clock; however, phase synchronization is not guaranteed. this clock can be placed into a high-impedance state, using the s_clkoff pin. pull-up resistors are not required on s_clko0; however, a series termination resistor is required when using this pin. a pull-up resistor may be required when s_clko0 is used as a result of s_clkoff=1, or disabled (clkcntrl[1:0]=11b; pci:68h), or disabled by pulling msk_in high. note: output clocks are not recommended for pci-x applications. external high-quality buffers are recommended. s_clko[4:1] secondary clock output 4 to 1 4oz l4, l5, k1, k2 provides p_clkin or oscin (if enabled) frequency output clocks; however, phase synchronization is not guar anteed. these clocks can be set to drive 0, using s_clkoff. when the s_clkoff pin is low, the associated clock control register disable bit (clkcntrl[8:0]; pci:68h) places the associated s_clko x pin into a high-impedance state. this function can be used when the disabled clock buffer is not connected to any device. pull-up resistors are not required on s_clko[4:1]; however, a series termination resistor is required when using these pins. s_clko[4:1] may require pull-up resistors if they are disabled by pulling msk_in high. note: output clocks are not recommended for pci-x applications. external high-quality buffers are recommended. table 3-6. clock-related pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-17 3?pin description s_clkoff secondary clock output disable 1pi k4 values: 0 = enables s_clko[4:0] output. this enable can be overridden by the clock control register disable bits (clkcntrl[8:0]; pci:68h). 1 = s_clko[4:1] output are disabled and driven low, and s_clko0 is placed into a high-impedance state. this disable cannot be overridden by the clock control register disable bits. may optionally be pulled high or low. note: msk_in can also be used to enable or disable s_clko[4:0]. s_cr secondary pll range control 1pi f5 selects the secondary pll operating range. must be pulled low for normal operation. pull or tie to v ss . s_pllen# secondary pll enable 1pi e6 values: 0 = enables secondary pll. 1 = disables secondary pll. pull or tie low or high, or connect to a 3.3v power supply. note: refer to section 4.6, ?pll and clock jitter,? for further detai ls regarding use in low frequency applications. total 18 table 3-6. clock-related pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-18 preliminary ? 2004 plx technology, inc. all rights reserved. table 3-7. reset pins symbol signal name total pins pin type pin number function p_rstin# primary reset input 1pi l2 when asserted, outputs are asynchronously placed into a high-impedance state, p_serr# and p_gnt# are floated, all primary pci signals are placed into a high-impedance state, and no bus parking is asserted. all primary port pci standard configuration registers at offsets 00h to 3fh revert to their default state. may require a pull-up resistor, depending on the application. pwrgd power good input 1pi n3 the asserting and de-asserting edges of pwrgd can be asynchronous to p_clkin and s_clkin. important note: the pci 6520 requires a clean low-to-high transition pwrgd input. pwrgd is not internally de-bounced?it must be externally de-bounced and a high input must reflect that the power is indeed stable. when this input is low, all pci 6520 state machines and registers are reset and all outputs, except s_rstout#, are placed into a high-impedance state. pull-up this input to 3.3v, rather than 5v. s_rstout# secondary reset output 1po h2 asserted when either of the following conditions is met: p_rstin# is asserted s_rstout# remains asserted if p_rstin# is asserted and does not de-assert until p_rstin# is de-asserted. bridge control register secondary reset bit in configuration space is set (bcntrl[6]=1; pci:3eh) s_rstout# remains asserted until bcntrl[6]=0. when asserted, places all control signals into a high-impedance state and drives s_ad[63:0], s_cbe[7:0]#, s_par, and s_par64 to a low logic level (0). total 3
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-19 3?pin description note: the jtag interface is described in section 22, ?testability/debug.? table 3-8. jtag/boundary scan pins symbol signal name total pins pin type pin number function tck test clock input 1 i pu y2 used to clock state information and test data into and out of the pci 6520 during test access port (tap) operation. pull tck high or low to a known state, using an external resistor. tdi test data input 1 i pu v4 used to serially shift test data and test instructions into the pci 6520 during tap operation. pull tdi high or low to a known state, using an external resistor. tdo test data output 1o w3 used to serially shift test data and test instructions out of the pci 6520 during tap operation. pull tdo high using an external resistor. tms test mode select 1 i pu u5 used to control the pci 6520 tap controller state. pull tms high or low to a known state, using an external resistor. trst# test reset 1 i pu y3 asynchronous jtag logic reset. provides asynchronous initialization of the tap controller. trst# must be externally pulled low with a 330-ohm resistor. total 5 table 3-9. serial eeprom pins symbol signal name total pins pin type pin number function eepclk serial eeprom clock 1po y5 clock signal to the serial eeprom interface. used during autoload and for vpd functions. eepdata serial eeprom data 1i/o y4 serial data interface to the serial eeprom. requires an external pull-up resistor. total 2
section 3 pin description pinout pci 6520cb data book, version 2.0 3-20 preliminary ? 2004 plx technology, inc. all rights reserved. note: the gpio pins are described in section 15, ?gpio interface.? table 3-10. general purpose i/o pins symbol signal name total pins pin type pin number function gpio[3:0] general purpose input/ output 3 to 0 4 i/o pu m5, m4, m2, m1 general purpose signal s, programmable as input-only or bi-directional by writing to the gpio output enable register (gpiooe[3:0]; pci:66h). during p_rstin# assertion, gpio[2, 0] are used to shift in the clock disable serial data. if configured as input, pull high or low, depending on the application. gpio[7:4] general purpose input/ output 7 to 4 4 i/o pu a5, b5, c5, d5 general purpose signal s, programmable as input-only or bi-directional by writing to the gpio output enable register (gpiooe[7:4]; pci:9eh). gpio[7:4] are internally pulled up. pcix100mhz pci-x 100 mhz 1 i/o a3 during s_rstout# assertion, pcix100mhz pin status is latched in and used in conjunction with the s_xcap_in pin to generate the secondary clock frequency value stored in the pci-x secondary status register (pcixssr[8:6]; pci:f2h). notes: recommended use: 100/ 133 mhz pci-x clock frequency. pull pcix100mhz low for all 133 mhz-capable applications. secondary pci-x clock maximum speed selection: 0 = 133 mhz. 1 = 100 mhz. refer to table 6-3, ?secondary clock frequency values (pcixssr[8:6]; pci:f2h),? on page 6-51 for further details. total 9
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-21 3?pin description table 3-11. miscellaneous pins symbol signal name total pins pin type pin number function bpcc_en bus/power clock control 1pi j2 when tied high and the pci 6520 is placed into the d 3hot power state, the pci 6520 places the secondary bus into the b 2 power state. the pci 6520 disables the secondary clocks and drives them to 0. when pulled low, placing the pci 6520 into the d 3hot power state has no effect on the secondary bus clocks. dev64# 64-bit device 1 pi w4 the inverse value of this input pin is reflected in pci-x bridge status register (pcixbsr[16]; pci:f4h). dev64# has no effect on bus transactions. values: 0 = 64-bit bus. 1 = 32-bit bus. may optionally be pulled high or low. p_clkrun# primary clock run 1i/o m17 used by the central resource (bus support functions supplied by the host system) to slow down or stop the pci clock when the clock is enabled. prv_dev private device and memory enable 1pi j4 after power-up, the functions set by prv_dev can be modified by software, using the chip control regi ster (ccntrl[3:2]; pci:40h). must be pulled high or low. when set to 1, the pci 6520 can mask secondary devices using idsel connected to s_ad[23:16] as private devices. any type 1 configuration access to these idsels is routed to s_ad24. if there is no device on s_ad24, the re-routed type 1 configuration cycles are master aborted. the pci 6520 also reserves private memory space for the secondary port. the memory space can be programmed using the private memory base and limit registers (base? pvtmbar; pci:6ch and pvtmbaru32; pci:70h, limit?pvtmlmt; pci:6eh and pvtmlmtu32; pci:74h). if the limit is smaller than the base, private memory space is disabled. the primary port cannot access this memory space through the bridge and the secondary port does not respond to memory cycles addressing this private memory space. p_tst[1:0] primary test 2 pi t14, t15 reserved inputs. connect p_tst[1:0] to logic 0 or 1 in layout for timing controls. (refer to the latest reference design information.) the recommended setting is p_tst[1:0]=1, 0. provide p_tst1 with the option of being pulled high. provide p_tst0 with the option of being pulled low.
section 3 pin description pinout pci 6520cb data book, version 2.0 3-22 preliminary ? 2004 plx technology, inc. all rights reserved. p_xcap primary port pci-x enable 1pi n2 values: 0 = primary port protocol is set by standard pci/pci-x reset initialization sequence. 1 = primary port is forced to run pci-x protocol. if the system host bus does not issue a pci-x initialization pattern, the primary port runs on pci protocol when p_xcap is pulled low. note: refer to section 3.2.7 for resistor requirements. s_cfn# internal arbiter enable 1pi h4 values: 0 = uses internal arbiter. 1 = uses external arbiter. s_req0# becomes req# output to external arbiter and s_gnt0# becomes external arbiter gnt# input. may optionally be pulled high or low; however, s_cfn# must be tied low to use the internal arbiter. s_clkrun# secondary clock run 1 i/o l18 when driven high, s_clkrun# slows down or stops the secondary pci clock and is driven by a secondary pci device to keep the clock running. s_tst[1:0] secondary test 2 pi e14, e15 reserved inputs. connect s_tst[1:0] to logic 0 or 1 in layout for timing controls. (refer to the latest reference design information.) the recommended setting is s_tst[1:0]=1, 0. provide s_tst1 with the option of being pulled high. provide s_tst0 with the option of being pulled low. table 3-11. miscellaneous pins (continued) symbol signal name total pins pin type pin number function
section 3 pinout pin description pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 3-23 3?pin description s_xcap_in secondary port pci-x enable 1pi n5 s_xcap_in is pulled high with 56k-ohm resistor and connected to s_xcap_pu by way of a 1k-ohm resistor. together with s_xcap_pu and pcix100mhz, s_xcap_in detects the secondary interface bus mode. if s_xcap_in is always sampled as 1 by the pci 6520 during secondary reset, the secondary port must run pci-x protocol. notes: refer to section 3.2.7 for additional resistor requirements. refer to table 6-3, ?secondary clock frequency values (pcixssr[8:6]; pci:f2h),? on page 6-51 for further details. s_xcap_pu secondary port pci-xcap pull-up 1oz h1 driven low by the pci 6520 for 32k secondary pci clocks before de-assertion to correctly detect pci-x bus mode configuration. a 1k-ohm resistor must be placed between s_xcap_pu and s_xcap_in. total 13 table 3-11. miscellaneous pins (continued) symbol signal name total pins pin type pin number function
section 3 pin description pinout pci 6520cb data book, version 2.0 3-24 preliminary ? 2004 plx technology, inc. all rights reserved. table 3-12. power, ground, and no connect pins symbol signal name total pins pin type pin number function p_av dd primary pll power 2i p6, r7 clean +1.8v for primary pll. p_v io primary system voltage 2i g1, p16 primary bus +3.3v system signaling environment voltage. note: refer to section 3.2.8 for external resistor implementation. p_av ss primary pll ground 2i p5, r6 clean ground for primary pll. s_av dd secondary pll power 2 i f7, g6 clean +1.8v for secondary pll. s_v io secondary system voltage 2 i e2, g16 secondary bus +3.3v system signaling environment voltage. note: refer to section 3.2.8 for external resistor implementation. s_av ss secondary pll ground 2 i f6, g5 clean ground for secondary pll. v dd_core core power 19 i e8, e13, f8, f13, g7, g14, h5, h6, h15, h16, n6, n15, n16, p7, p14, r8, r13, t8, t13 +1.8v supply for digital core. v dd_io i/o ring power 35 i c3, c15, c18, f9, f10, f11, f12, f18, g8, g13, h7, h14, j6, j15, k6, k15, l3, l6, l15, m6, m15, n7, n14, p8, p13, r3, r9, r10, r11, r12, r18, v3, v6, v15, v18 +3.3v for digital i/o buffers. v ss ground 51 i a1, a8, a20, c9, c12, e5, e16, g9, g10, g11, g12, j3, j7, j9, j10, j11, j12, j14, j18, k7, k9, k10, k11, k12, k14, l7, l9, l10, l11, l12, l14, m3, m7, m9, m10, m11, m12, m14, m18, p9, p10, p11, p12, t5, t16, v9, u6, v12, w5, y1, y20 ground for digital core and i/o. nc no connect 24 ? a2, a4, b2, b3, b4, c4, d4, e7, f14, f15, f16, g15, h3, l1, l17, m19, p15, r14, r15, r16, u7, v5, w6, y6 no connect pins, which are not to be connected or used as routing channels. may be used in future pci 6520 revisions. total 141
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 4-1 4?clocking 4 clocking this section describes the pci 6520 clocking requirements. to correctly operate, the pci 6520 requires both a primary and secondary clock. 4.1 primary and secondary clock inputs the pci 6520 implements a separate clock input for each pci interface. the primary interface is synchronized to the primary clock input, p_clkin. the secondary interface is synchronized to the secondary clock input, s_clkin. the pci 6520 primary and secondary clock inputs can be asynchronous. there are no skew constraints between these clock inputs; however, the maximum ratio between the primary and secondary clock frequencies are 1:4 or 4:1. the pci 6520 operates at a maximum frequency of 133 mhz. output clocks s_clko[4:0] can be derived from p_clkin, p_clkin/2, or an external asynchronous clock source. 4.2 secondary clock outputs note: the pci 6520 s_clko[4:0] outputs are not recommended for pci-x use. use high-quality clock buffers for pci-x applications. the pci 6520 has five secondary clock outputs that can be used to drive up to four external secondary bus devices. typically, s_clko0 or s_clko4 is used to drive the pci 6520 s_clkin signal. the rules for using secondary clocks are as follows: each secondary clock output is limited to no more than one pci device. the pci 6520 can drive one load in an embedded system or two loads when driving an adapter card slots ( that is , the connector plus the adapter card). each clock trace length, including the feedback clock to the pci 6520 s_clkin signal, must have equal length and impedance. terminate or disable unused secondary clock outputs to reduce power dissipation and noise in the system. 4.2.1 disabling secondary clock outputs secondary clock outputs may be disabled in two ways. if the s_clkoff input is asserted (high), s_clko0 is placed into a high-impedance state and s_clko[4:1] are disabled and driven low. the clock control register (clkcntrl; pci:68h) allows individual clock outputs to be disabled. clock outputs disabled by clkcntrl remain disabled, regardless of s_clkoff status. 4.2.2 secondary clock control the pci 6520 uses the gpio[2, 0] pins and msk_in signal to input a 16-bit serial data stream. this data stream is shifted into the clock control register, as soon as p_rstin# is detected de-asserted and s_rstout# is detected, and is used for selectively disabling s_clko[4:0] (clkcntrl[8:0]; pci:68h). s_rstout# de-assertion is delayed until the pci 6520 completes shifting in the clock mask data, taking 16 clock cycles (32 cycles if operating at 66 mhz). after that, the gpio[2, 0] pins can be used as general purpose i/o pins. an external shift register should be used to load and shift the data. (refer to figure 4-1.) the gpio[2, 0] pins are used for shift register control and serial data input, which occurs by way of a dedicated input signal, msk_in. the shift register circuitry is unnecessary for correct pci 6520 operation. the shift registers may be eliminated and, if s_clkoff is low, msk_in can be tied low to enable all s_clko[4:0] signals, or tied high to disable all s_clko[4:0] signals to three-state. if s_clko[4:0] are disabled to three-state, then it is recommended that pull-up resistors be added to the s_clko[4:0] pins to prevent noise from coupling into the pci 6520. table 4-1 delineates gpio[2, 0] pin shift register operation and table 4-2 delineates serial data formatting, based on a design where the pci 6520 secondary bus is used to drive up to four pci adapter card slots or five devices in an embedded system.
section 4 clocking secondary clock outputs pci 6520cb data book, version 2.0 4-2 preliminary ? 2004 plx technology, inc. all rights reserved. figure 4-1. gpio clock mask implem entation on system board example notes: * pulling the upper 74f166 bit 0 low enables s_clko4. in the philips 74f166 prsntx# signals, x indicates the slot number, and the number in brackets indicates the appropriate prsnt# signal (for example, prsnt0[1]# is signal prsnt1# of slot 0). figure 4-2. clock mask and load shift timing pci 6520 q7 74f166 q7 74f166 msk_in gpio0 gpio2 v ss v cc v ss v cc ce# cp mr# pe 7 6 5 4 3 2 1 0 ce# cp mr# pe 7 6 5 4 3 2 1 *0 prsnt3[2]# prsnt3[1]# prsnt2[2]# prsnt2[1]# prsnt1[2]# prsnt1[1]# prsnt0[2]# prsnt0[1]# d s bit 15 bit 14 bit 13 bit 12 bit 11 gpio0 gpio2 msk_in
section 4 secondary clock outputs clocking pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 4-3 4?clocking as noted in table 4-2, the first eight bits contain the philips 74f166 prsnt x [2:1]# signal (refer to figure 4-1) values for four slots, and control s_clko[3:0]. if one or both of the prsnt x [2:1]# signals are 0, a card is present in the slot and the secondary clock for that slot is not masked. if these clocks are connected to devices and not to slots, tie one or both of the bits low, to enable the clock. the ninth bit is a clock device mask ( that is , the bit enables or disables the clock for one device). this bit controls s_clko4?a value of 0 enables the clock, and 1 disables the clock. if desired, the assignment of s_clko x to slots, devices, and pci 6520 s_clkin input can be re-arranged from the assignment noted here. however, it is important that the serial data stream format match the assignment of s_clko x . the gpio[2, 0] pin serial protocol is designed to work with two philips 74f166, 8-bit bi-directional universal shift registers. figure 4-1 illustrates an example application where the pci 6520 is connected to four pci adapter card slots. the prsnt x [2:1]# pin values on the 74f166 devices are shifted into clkcntrl[7:0]. the prsnt0[1]# value is shifted into clkcntrl[0], prsnt0[2]# value is shifted into clkcntrl[1], and so forth. bit 0 in the upper 74f166 is tied low, and thus enables s_clko4. in this application, s_clko4 may be used as the feedback to s_clkin. when s_rstout# is detected asserted and p_rstin# is detected de-asserted, the pci 6520 drives gpio2 low for one cycle to load the clock mask inputs into the shift register. on the next cycle, the pci 6520 drives gpio2 high to perform a shift operation. this shifts the clock mask into msk_in; the most significant bit is shifted in first, and the least significant bit is shifted in last. (refer to figure 4-2.) after the shift operation is complete, the pci 6520 places gpio[2, 0] into a high-impedance state and can de-assert s_rstout# if the secondary reset bit is clear (bcntrl[6]=0; pci:3eh). the pci 6520 then ignores msk_in, and gpio signal control reverts to the pci 6520 gpio control registers. the clock disable bits can be subsequently modified through a configuration write command to the clock control register (clkcntrl) in device-specific configuration space. table 4-1. gpio shift register operation pin operation gpio0 shift register clock output at 66 mhz maximum frequency. gpio1 not used. gpio2 shift register control. values: 0 = load 1 = shift gpio3 not used. table 4-2. gpio serial data format clkcntrl[15:0] description s_clko[4:0] 1:0 slot 0 74f166 prsnt0[2:1]# or device 0 0 3:2 slot 1 74f166 prsnt1[2:1]# or device 1 1 5:4 slot 2 74f166 prsnt2[2:1]# or device 2 2 7:6 slot 3 74f166 prsnt3[2:1]# or device 3 3 8 device 4 4 15:9 reserved ?
section 4 clocking using an external clock source pci 6520cb data book, version 2.0 4-4 preliminary ? 2004 plx technology, inc. all rights reserved. 4.3 using an external clock source s_clkin_stb input allows for an indication that the secondary external clock source is stable. if this input is de-asserted (low), then this indicates that the s_clkin signal is not yet stable. the pci 6520 does not de-assert s_rstout# until s_clkin_stb is asserted (high). this ensures that a valid and stable secondary clock source is present before transactions can occur on the secondary bus. the pci 6520 uses two signals?oscsel# and oscin?when connecting an external clock source to the pci 6520. during normal operation, the pci 6520 generates s_clko[4:0] outputs, based on the pci clock source (p_clkin). if oscsel# is asserted (low), then the pci 6520 derives s_clko[4:0] from the oscin signal instead. clock division is performed on the oscin and p_clkin clocks, depending on the p_m66en and s_m66en signal states. 4.4 frequency division options the pci 6520 has built-in frequency division options to automatically adjust the s_clko[4:0] clocks for pci 33 or 66 mhz operations. for pci-x applications, use external, high-quality clock buffers and dividers. table 4-3 lists the clock division ratios used, depending on the p_m66en and s_m66en signal states. note: s_m66en cannot be floating. 4.5 running secondary port faster than primary port the pci 6520 allows the secondary port to use a higher clock frequency than that of the primary port. in this case, a secondary clock source, using an external oscillator or clock generator, must be provided. if the external oscillator is connected to oscin and oscsel# is asserted (low), then the output generated by s_clko[4:0] is divided, as per table 4-3. division control can be disabled by pulling s_m66en high and not connecting this pin to a pci slot (which may be on the secondary bus). if the s_clko[4:0] outputs are not required, then the external clock can be fed directly into the s_clkin signal. 4.6 pll and clock jitter the pci 6520 uses two plls, one for each interface. these plls can be individually disabled by connecting the p_pllen# or s_pllen# pin to 1. the minimum input frequency of each pll is 50 mhz. if a pci 6520 port is used in a low-speed application ( for example, at 33 mhz), then disable the appropriate pll by setting p_pllen# or s_pllen# to high. for typical adapter card designs, use the adapter card?s m66en pin to control the pci 6520?s primary pll by connecting the input of an inverter to the m66en pin and the output to the pci 6520?s p_pllen# input. this ensures that the primary pll is disabled when operating at 33 mhz. a similar method may be required to control the secondary pll, depending on the application. the pci 6520 uses the pci-x initialization pattern to automatically enable or disable the primary pll. pci-x r1.0b , table 6-1 (extrapolated in table 4-4), defines an add-in card?s capabilities according to its pci-xcap and m66en signal states. the primary pll is enabled or disabled when p_pllen# is pulled low, as listed in table 4-4. the pll is sensitive to power and ground noise. a dedicated set of pll power and ground pins are provided to reduce power and ground bounce caused by digital logic feeding into the plls. connect the av dd pins for each pll to a clean +1.8v supply and de-couple to the appropriate ground pins. table 4-5 details the pll operational parameters for the primary and secondary plls. table 4-3. pci clock frequency division ratios p_m66en value s_m66en value pci clock frequency division ratio 111/1 101/2 011/1 001/1
section 4 pll and clock jitter clocking pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 4-5 4?clocking table 4-4. m66en and pci-xcap encoding m66en pci-xcap conventional pci device frequency capability pci-x device frequency capability primary pll enabled ground ground 33 mhz not capable no 10k-ohm pull-down resistor pci-x 66 mhz yes not connected pci-x 133 mhz not connected ground 66 mhz not capable yes 10k-ohm pull-down resistor pci-x 66 mhz not connected pci-x 133 mhz table 4-5. pll and clock jitter parameters parameter minimum typical maximum unit condition input frequency 50 ? 133 mhz ? input rise and fall time ? ? 500 ps ? input cycle-to-cycle jitter -100 ? +100 ps ? input jitter modulation frequency must be < 100 khz to allow pll tracking or > 30 mhz to allow pll filtering output cycle-to-cycle jitter -150 ? +150 ps clean power v dd = 1.8v output duty cycle 45 ? 55 % clean power v dd = 1.8v phase lock time ? ? 100 s clean power v dd = 1.8v pll power dissipation ? 9 25 mw clean power v dd = 1.8v f in = f out = 133 mhz operating ambient temperature -40 ? +85 c ?
section 4 clocking detecting pci bus speed with the reference clock pci 6520cb data book, version 2.0 4-6 preliminary ? 2004 plx technology, inc. all rights reserved. 4.7 detecting pci bus speed with the reference clock the pci 6520 has a reference clock input, refclk, which is used by a timer. any fixed-frequency source can be used as a reference clock source, although 14.318 mhz is recommended. the timer can be set to time the primary or secondary port clock inputs (p_clkin or s_clkin, respectively). the timer control register controls the count period and the pci clock to be timed (tmrcntrl[7:4 and 2:1]; pci:61h, respectively). software can then read the timer value from the timer counter register (tmrcnt; pci:62h) and calculate the corresponding port?s clock frequency. 4.8 primary or secondary clock frequency measurement refclk is used with the timer control and timer counter registers (tmrcntrl; pci:61h and tmrcnt; pci:62h, respectively) to measure the approximate bus frequency on the primary or secondary interface. the refclk clock frequency should be significantly slower than that of the primary and secondary clocks. software must select the target bus, using bit 1 of the timer counter clock source select bits (tmrcntrl[2:1]; pci:61h). note that tmrcntrl[2] is always cleared to 0. software sets the timer enable bit to start the measurement (tmrcntrl[0]=1; pci:61h). tmrcntrl[0] remains set, and software polls the timer stop bit until the bit is set to 1 (tmrcntrl[3]=1; pci:61h). when tmrcntrl[3]=1, the measurement is complete and the result is presented in the timer counter register. to start a new measurement, the software must set tmrcntrl[0] to 0, and then 1. the measurement process counts the total measured bus clock rising edges that occurred during the overall count period. the counter, however, accumulates only the bus clock rising edges that occurred during the high states of each reference clock cycle. the count period (tmrcntrl[5:4]) values indicate the number of high states used to accumulate the count (16, 32, 64, or 128). the total number of rising edges in all high states are accumulated and reported in the timer counter register. for example, if a reference clock speed of 14.318 mhz is used, the size of each reference clock high state is (1 / 14.318m) / 2 = 349 ns. the timer counter register stores the accumulated count of rising edges within the count period. when the measurement is finished (indicated by tmrcntrl[3]=1), the tmrcnt register value can be used to determine the approximate bus speed. example: reference clock speed = 14.318 mhz measured clock = secondary bus clock count period (number of windows; tmrcntrl[5:4]=00b) = 16 secondary bus speed = 66 mhz based on this configuration, tmrcntrl[1] is set to 1 because the secondary bus clock is the measured clock. tmrcntrl[5:4] are set to 00b for 16 high states. the software first writes 0 to tmrcntrl[0] (assuming there is a previous measurement), then writes 1 to start the measurement. software polls tmrcntrl[3] until the bit is set to 1. expected timer counter count for this example: because the reference clock is 14.318 mhz, each window size is about 349 ns. if the measured clock speed is 66 mhz, the clock period is about 15 ns. therefore, each window count is 23 or 24 (349 / 15). because 16 windows (high states) were opened, the total count is in the range of 23 x 15 = 345 and 24 x 15 = 360. note: for further details, refer to the tmrcntrl and tmrcnt registers in section 6, ?registers.?
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 5-1 5?reset and initialization 5 reset and initialization this section describes pci-xcap connections and operating frequency, secondary bus mode and frequency initialization, conventional pci mode 66 mhz operation, reset, and register initialization. 5.1 pci-xcap connections and operating frequency the pci 6520 operates at up to 66 mhz in conventional pci mode and up to 133 mhz in pci-x mode. the primary and secondary ports each have a pci-xcap input (p_xcap and s_xcap_in, respectively) that determines whether it is configured as a pci or pci-x port. pci-xcap is also used to determine the operating frequency of ports operating in pci-x mode. 5.1.1 primary port pci-xcap connection in a standard adapter card design, configure the p_xcap pin as detailed in pci-x r1.0b , section 6.2. there may be situations, however, where the standard pci-x reset and initialization sequence is not available. for example, this may be the case during a compactpci hot swap device insertion. to force the primary port to use pci-x protocol, set the p_xcap input to 1. if p_xcap is set to 0, the primary port is configured to use pci protocol and standard pci reset and initialization occurs. 5.1.2 secondary port pci-xcap connection two pci 6520 pins are associated with the secondary pci-xcap connection?s_xcap_in and s_xcap_pu. the s_xcap_in pin is used to determine whether secondary devices are capable of pci-x operation and at what frequency the devices can operate. connect s_xcap_in to a weak 56k-ohm resistor, pulled up to 3.3v, and to the pci-xcap pin on secondary pci-x slots. connect s_xcap_pu output and s_xcap_in together with a 1k-ohm resistor. during pci-x and frequency discovery on the secondary bus, the s_xcap_pu signal is driven low for 32k secondary pci clocks and provides a strong pull-up resistor. this allows capacitors attached to pci-x adapter card pci-xcap pins to charge. the pci 6520 can then determine whether pci-x cards are attached to the secondary port. if pci-x and frequency discovery are not required, set s_xcap_in to 1 to force pci-x transactions to occur on the secondary bus, or to 0 to force conventional pci transactions. 5.2 secondary bus mode and frequency initialization sequence the pci 6520 places its secondary bus in pci-x mode based on the capabilities of devices connected to the secondary bus, independent of the primary bus mode. if only one side of a bridge is operating in pci-x mode, the pci 6520 translates the protocol between the two buses. at the rising edge of p_rstin#, the pci 6520 latches the frequency and mode of its primary bus. the pci 6520 initializes the secondary bus as follows: 1. senses the s_xcap_in and s_m66en state for all devices on the secondary bus and selects the appropriate mode and clock frequency. when the secondary bus: includes one or more 33 mhz conventional pci devices, the bus operating frequency must be conventional pci 33 mhz. includes only conventional pci 66 mhz devices, the operating frequency is 66 mhz. includes only pci-x 66 devices, the maximum clock frequency is 66 mhz. includes only pci-x 100 devices, the maximum clock frequency is 100 mhz. 100 mhz selection status can be configured using the pcix100mhz pin. includes only pci-x 133 devices, the maximum clock frequency is 133 mhz. 2. asserts the appropriate signals for the pci-x initialization pattern on the secondary bus. 3. de-asserts s_rstout# to place all devices on the secondary bus in the appropriate mode.
section 5 reset and initialization conventional pci mode 66 mhz operation pci 6520cb data book, version 2.0 5-2 preliminary ? 2004 plx technology, inc. all rights reserved. 5.3 conventional pci mode 66 mhz operation the p_m66en and s_m66en signals indicate whether the primary and secondary interfaces are operating at 66 mhz. this information is needed to control the secondary bus frequency. pci r2.3 prohibits pci clock frequency changes above 33 mhz, except during a pci reset. the following primary and secondary bus frequency combinations are supported when using the primary p_clkin signal to generate secondary clock outputs: 66 mhz primary bus, 66 mhz secondary bus 66 mhz primary bus, 33 mhz secondary bus 33 mhz primary bus, 33 mhz secondary bus if p_m66en is low ( for example , the primary bus runs at 33 mhz), the pci 6520 drives s_m66en low to indicate that the secondary bus is operating at 33 mhz. if the secondary bus is set to run faster than the primary bus, s_m66en need not be connected to secondary pci devices. the pci 6520 can also generate s_clko[4:0] outputs from oscin, if enabled. when the pci 6520 is using asynchronous clock inputs ( for example, s_clko[4:0] are not derived from p_clkin or oscin), the previously listed frequencies are not the only possible clock combinations. if an external clock is used for the secondary interface, the pci 6520 operates with a maximum ratio of 1:4 or 4:1 between the primary and secondary bus clocks. for further details, refer to section 4.4, ?frequency division options,? and section 4.5, ?running secondary port faster than primary port.? 5.4 reset this subsection describes the primary and secondary interface, and chip reset mechanisms. the pci 6520 has two reset inputs?pwrgd and p_rstin#?and one reset output?s_rstout#. in addition, the pci 6520 can respond to power management-initiated and software-controlled internal resets. after the reset signals are de-asserted, the pci 6520 requires 512 clocks to initialize bridge functions. during this initialization, type 0 accesses can be accepted. 5.4.1 power good reset when pwrgd is not active, the following occurs: 1. pci 6520 immediately places all primary pci-x interface signals into a high-impedance state. 2. pci 6520 performs a full chip reset. 3. s_rstout# is asserted (low). 4. all registers and extended registers with default values are reset. 5. if p_rstin# is low, pwrgd going from low-to-high causes the serial eeprom to be loaded. note: the pci 6520 requires a clean low-to-high transition for pwrgd input. the pwrgd signal is not internally de-bounced?it must be externally de-bounced and a high input must reflect that the power is stable. the asserting and de-asserting edges of pwrgd can be asynchronous to p_clkin and s_clkin. usually, pwrgd should not change to low when p_rstin# is high. if p_rstin# is de-asserted before pwrgd assertion, the primary pci-x signals remain in a high-impedance state because pwrgd is not asserted. s_rstout# remains asserted until a few clocks after pwrgd assertion. when pwrgd is de-asserted, all primary and secondary pci signals are placed into a high-impedance state. s_rstout# remains asserted until pwrgd is asserted. (refer to timing diagram 5-1.)
section 5 reset reset and initialization pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 5-3 5?reset and initialization timing diagram 5-1. pwrgd assertion 5.4.2 primary reset input to properly reset, the pci 6520 requires at least two clocks before the p_rstin# rising edge. when p_rstin# is asserted, the following events occur: 1. pci 6520 immediately places all primary pci interface signals into a high-impedance state. 2. all registers are reset. 3. s_rstout# is driven active to indicate a primary pci reset. 4. p_rstin# assertion automatically causes a secondary port reset and s_rstout# assertion. s_trdy#, s_devsel#, and s_stop# are driven for pci-x speed inquiry. 5. clock disable bits (clkcntrl[8:0]; pci:68h) are shifted in at p_rstin# de-assertion. the asserting and de-asserting edges of p_rstin# can be asynchronous to p_clkin and s_clkin. when p_rstin# is asserted, all primary pci interface signals, including the primary request output, are immediately placed into a high-impedance state. all posted write and delayed transaction data buffers are reset. therefore, transactions residing in the buffers are discarded upon p_rstin# assertion. 5.4.3 secondary reset output the pci 6520 is responsible for driving the secondary bus reset signal, s_rstout#. the pci 6520 asserts s_rstout# when one of the following conditions is met: p_rstin# is asserted. s_rstout# remains asserted when one of the following conditions is met: secondary clock serial disable mask (clkcntrl[8:0]; pci:68h) is being shifted in (16 clock cycles after p_rstin# de-assertion), using msk_in and gpio[2, 0] s_clkin_stb is low diagnostic control register chip reset and bridge control secondary reset bits are set (dcntrl[0]=1; pci:41h and bcntrl[6]=1; pci:3eh, respectively). s_rstout# remains asserted until the secondary reset output mask bit is cleared (dcntrl[3]=0; pci:41h). when there is a d 3hot -to-d 0 transition with the power management control/status register power state bits programmed to d 0 (pmcsr[1:0]=00b; pci:e0h), s_rstout# is active for 16 primary port pci clock cycles. while s_rstout# is asserted, s_devsel#, s_stop#, and s_trdy# are driven for pci-x speed inquiry. (refer to table 5-2 for status of all affected signals.) pwrgd p/s_pci-x signals s_rstout# power not good power good high-impedance state normal state
section 5 reset and initialization reset pci 6520cb data book, version 2.0 5-4 preliminary ? 2004 plx technology, inc. all rights reserved. 5.4.4 jtag reset refer to section 22.1.4, ?jtag reset input trst#.? 5.4.5 software resets the diagnostic control register chip reset bit can be used to reset the pci 6520 as the pwrgd input (dcntrl[0]=1; pci:41h). this action causes s_rstout# assertion; however, the signals are not placed into a high-impedance state. when the chip reset bit is set, all registers and chip states are reset. when chip reset completes, within four pci clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the pci 6520 is ready for configuration. during chip reset, the pci 6520 is inaccessible. 5.4.6 power manageme nt internal reset when there is a d 3hot -to-d 0 transition with the power management control/status register power state bits programmed to d 0 (pmcsr[1:0]=00b; pci:e0h), an internal reset equivalent to p_rstin# is generated and all relevant registers are reset. however, s_rstout# is not asserted. 5.4.7 reset inputs effect on pci 6520 other reset controls can be used to generate secondary reset output. table 5-1 depicts the effect of various reset inputs on the pci 6520. table 5-1. reset input effect on pci 6520 reset inputs effect p_rstin# resets primary and secondary ports asserts s_rstout# causes serial eeprom load s_clk_stb not active resets only secondary port asserts s_rstout# pwrgd not ready asserts s_rstout# causes serial eeprom load chip reset (dcntrl[0]=1; pci:41h) resets internal state machines secondary reset (bcntrl[6]=1; pci:3eh) asserts s_rstout#
section 5 reset reset and initialization pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 5-5 5?reset and initialization 5.4.8 pin states during pwrgd and primary reset the pci 6520 supports pwrgd and p_rstin#. table 5-2 depicts the pin state for each event. with the exception of the power not good state (pwrgd=0), all states assume a valid input clock. legend : u = undetermined i = input only t = placed into a high-impedance state d1 = drive 1 to output d0 = drive 0 to output d01 = can drive both 0 or 1 to output table 5-2. pin states during pwrgd and p_rstin# power-up/reset pci 6520 pins pwrgd=0, with or without clock, p_rstin#=x pwrgd=1 and p_rstin#=0 power-up/reset pci 6520 pins pwrgd=0, with or without clock, p_rstin#=x pwrgd=1 and p_rstin#=0 bpcc_en i i p_v io ii dev64# i i pwrgd i i eepclk no p_clkin: u with p_clkin: d1 d1 refclk i i eepdata no p_clkin: u with p_clkin: d1 d1 s_ack64# t t gpio0 d1 d1 s_ad[63:0] t d0 gpio[2:1] d0 d0 s_av dd ii gpio[7:3} t t s_av ss ii msk_in i i s_cbe[7:0]# t d0 oscin i i s_cfn# i i oscsel# i i s_clkin i i p_ack64# t t s_clkin_stb i i p_ad[63:0] t t s_clko[4:0] - s_clkoff=0 - s_clkoff=1 d01 d0 d01 d0 p_av dd iis_clkoffii p_av ss i i s_clkrun# d0 p_cbe[7:0]# t t s_cr i i pcix100mhz t t s_devsel# t t (pci) d01 (pci-x) p_clkin i i s_frame# t t
section 5 reset and initialization reset pci 6520cb data book, version 2.0 5-6 preliminary ? 2004 plx technology, inc. all rights reserved. p_clkoe i i s_gnt0# t d1 p_clkrun# i i s_gnt[7:1]# t d1 p_cr i i s_irdy# t t p_devsel# t t s_lock# t t p_frame# t t s_m66en# i i p_gnt# i i s_par t d0 p_idsel i i s_par64 t d0 p_irdy# t t s_perr# t t p_lock# t t s_pllen# i i p_m66en# i i s_req0# t i p_par t t s_req[7:1]# i i p_par64 t t s_req64# t d0 p_perr# t t s_rstout# d0 d0 p_pllen# i i s_serr# t t p_req# t t s_stop# t t (pci) d01 (pci-x) p_req64# t t s_trdy# t t (pci) d01 (pci-x) p_rstin# i i s_tst[1:0] i i prv_dev i i s_v io ii p_serr# t t s_xcap_in i i p_stop# t t s_xcap_pu i i p_trdy# t t v dd_core ii p_tst[1:0] i i v dd_io ii p_xcap i i v ss ii table 5-2. pin states during pwrgd and p_rstin# (continued) power-up/reset pci 6520 pins pwrgd=0, with or without clock, p_rstin#=x pwrgd=1 and p_rstin#=0 power-up/reset pci 6520 pins pwrgd=0, with or without clock, p_rstin#=x pwrgd=1 and p_rstin#=0
section 5 register initialization reset and initialization pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 5-7 5?reset and initialization 5.5 register initialization the pci 6520 configuration registers may be initialized in one of three ways: default values serial eeprom contents host initialization 5.5.1 default initialization after p_rstin# de-assertion or pwrgd assertion (whichever occurs later), the pci 6520 automatically checks for a valid a serial eeprom. if the serial eeprom is not valid nor present, the pci 6520 automatically loads default values into the configuration registers. (refer to the ?value after reset? column of the register tables in section 6, ?registers.?) 5.5.2 serial eeprom initialization after p_rstin# de-assertion or pwrgd assertion (whichever occurs later), if the pci 6520 finds a valid serial eeprom, register values are loaded from the serial eeprom and overwrite the default values. (refer to section 7.3, ?serial eeprom autoload mode at reset.?) 5.5.3 host initialization when device initialization is complete, the host system may access the appropriate registers to configure them according to system requirements. typically, registers are accessed by performing type 0 configuration accesses from the appropriate bus. the exceptions to this are the extended registers, which are accessed using the extended register index and data registers (extridx; pci:d3h and extrdata; pci:d4h, respectively). for details regarding register access, refer to section 6, ?registers.? note: not all registers may be written to nor available from both sides of the bridge.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-1 6?registers 6 registers this section describes the pci 6520 pci and pci-x registers. as a transparent pci-x bridge, the pci 6520 includes the standard type 01h configuration space header as defined in p-to-p bridge r1.2 . in conventional pci mode, these registers operate as defined in this specification. if either pci 6520 interface is initialized to pci-x mode, the requirements for these registers change to meet those of pci-x r1.0b , section 8.6. note: registers listed with a pci of fset or address are accessed by standard pci type 0 configuration accesses.
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-2 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1 pci configuration register addre ss mapping table 6-1. pci configuration register address mapping pci configuration register address to ensure software compatibility with other versions of the pci 6520 family and to ensure compatibility with future enhancements, write 0 to all unused bits. pci writable serial eeprom writable 31 24 23 16 15 8 70 00h device id* vendor id* yes yes 04h primary status primary command yes no 08h class code* revision id yes yes 0ch built-in self-test (not supported) header type* primary latency timer cache line size yes yes 10h ? 14h reserved no no 18h secondary latency timer subordinate bus number secondary bus number primary bus number yes no 1ch secondary status i/o limit i/o base yes no 20h memory limit memory base yes no 24h prefetchable memory limit prefetchable memory base yes no 28h prefetchable memory base upper 32 bits yes no 2ch prefetchable memory limit upper 32 bits yes no 30h i/o limit upper 16 bits i/o base upper 16 bits yes no 34h reserved new capability pointer no no 38h reserved no no 3ch bridge control interrupt pin reserved yes no 40h arbiter control diagnostic control chip control yes no 44h miscellaneous options timeout control primary flow-through control yes yes 48h secondary incremental prefetch count primary incremental prefetch count secondary initial prefetch count primary initial prefetch count yes yes 4ch buffer control secondary flow-through control secondary maximum prefetch count primary maximum prefetch count yes yes 50h reserved test internal arbiter control yes no 54h serial eeprom data serial eeprom address serial eeprom control yes no 58h reserved no no 5ch reserved no no 60h timer counter timer control reserved yes no 64h gpio[3:0] input data gpio[3:0] output enable gpio[3:0] output data p_serr# event disable yes no 68h clock run p_serr# status clock control yes no 6ch private memory limit private memory base yes no 70h private memory base upper 32 bits yes no 74h private memory limit upper 32 bits yes no 78h ? 98h reserved no no
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-3 6?registers notes: * writable only when the read-only registers write enable bit is set (rrc[7]=1; pci:9ch). refer to the individual register descriptions to deter mine which bits are writable. refer to the individual register descriptions to determine which bits are writable. 9ch gpio[7:4] input data gpio[7:4] output enable gpio[7:4] output data read-only register control yes no a0h reserved no no ach ? cch reserved no no d0h extended register index reserved yes no d4h extended register data yes no d8h reserved no no dch power management capabilities power management next capability pointer (e8h) power management capability id (01h) yes yes e0h power management data* pmcsr bridge supports extensions power management control/status* yes yes e4h reserved no no e8h vpd address (0h) vpd next capability pointer (f0h) vpd capability id (03h) yes no ech vpd data (0h) yes no f0h pci-x secondary status pci-x next capability pointer (0h) pci-x capability id (07h) yes no f4h pci-x bridge status yes no f8h pci-x upstream split transaction yes no fch pci-x downstream split transaction yes no table 6-1. pci configuration register address mapping (continued) pci configuration register address to ensure software compatibility with other versions of the pci 6520 family and to ensure compatibility with future enhancements, write 0 to all unused bits. pci writable serial eeprom writable 31 24 23 16 15 8 70
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-4 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.1 pci type 1 header register 6-1. (pciidr; pci:00h) pci configuration id bit description read write value after reset 15:0 vendor id. identifies pci 6520 manufacturer. defaults to the pci-sig-issued plx vendor id (10b5h), if a blank or no serial eeprom is present. yes only if rrc[7]=1; serial eeprom 10b5h 31:16 device id. identifies the particular device. defaults to plx pci 6520 part number (6520h), if a blank or no serial eeprom is present. yes only if rrc[7]=1; serial eeprom 6520h register 6-2. (pcicr; pci:04h) primary pci command bit description read write value after reset 0 i/o space enable. controls bridge response to i/o accesses on primary interface. values: 0 = ignores i/o transactions 1 = enables response to i/o transactions yes yes 0 1 memory space enable. controls bridge response to memory accesses on primary interface. values: 0 = ignores memory transactions 1 = enables response to memory transactions yes yes 0 2 bus master enable. controls bridge ability to operate as a master on primary interface. values: 0 = does not initiate transactions on primary interface and disables response to memory or i/o transactions on secondary interface 1 = enables bridge to operate as a master on primary interface yes yes 0 3 special cycle enable. not supported. yes no 0 4 memory write and invalidate enable. not supported. yes no 0 5 vga palette snoop enable. controls bridge response to vga-compatible palette accesses. values: 0 = ignores vga palette accesses on primary interface 1 = enables response to vga palette writes on primary interface (i/o address ad[9:0]=3c6h, 3c8h, and 3c9h) note: if bcntrl[3]=1; pci:3eh (vga enable bit), then vga palette accesses are forwarded, regardless of the pcicr[5] value. yes yes 0 6 parity error response enable. controls bridge response to parity errors. values: 0 = ignores parity errors 1 = performs normal parity checking yes yes 0 7 wait cycle control. if set to 1, the pci 6520 performs address/data stepping. yes yes 1
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-5 6?registers 8 p_serr# enable. controls the primary system error (p_serr#) pin enable. values: 0 = disables p_serr# driver 1 = enables p_serr# driver yes yes 0 9 fast back-to-back enable. controls bridge ability to generate fast back-to-back trans actions to various devices on primary interface. values: 0 = no fast back-to-back transactions 1 = reserved ; pci 6520 does not generate fast back-to-back cycles yes yes 0 15:10 reserved. yes no 0h register 6-2. (pcicr; pci:04h) primary pci command (continued) bit description read write value after reset register 6-3. (pcisr; pci:06h) primar y pci status bit description read write value after reset 3:0 reserved. yes no 0h 4 new capability functions support. writing 1 supports new capabilities functions. the new capability function id is located at the pci configuration space offset, determined by the new capabilities linked list pointer value at cap_ptr; pci:34h. yes no 1 5 66 mhz-capable. if set to 1, this device supports a 66 mhz pci clock environment. yes no 1 6 udf. no user-definable features. yes no 0 7 fast back-to-back capable. fast back-to-back write capable on primary port. yes no 0 8 data parity error detected. set when the following conditions are met: p_perr# is asserted, and command register parity error response enable bit is set (pcicr[6]=1; pci:04h) writing 1 clears bit to 0. yes yes/clr 0 10:9 devsel# timing . reads as 01b to indicate pci 6520 responds no slower than with medium timing. yes no 01b 11 signaled target abort. set by a target device when a target abort cycle occurs. writing 1 clears bit to 0. yes yes/clr 0 12 received target abort. set to 1 by the pci 6520 when transactions are terminated with target abort. writing 1 clears bit to 0. yes yes/clr 0 13 received master abort. set to 1 by the pci 6520 when transactions are terminated with master abort. writing 1 clears bit to 0. yes yes/clr 0 14 signaled system error. set when p_serr# is asserted. writing 1 clears bit to 0. yes yes/clr 0 15 parity error detected. set when a parity error is detected, regardless of the parity error response enable bit state (pcicr[6]=x; pci:04h). writing 1 clears bit to 0. yes yes/clr 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-6 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-4. (pcirev; pci:08h) pci revision id bit description read write value after reset 7:0 revision id. pci 6520 revision. yes no cbh register 6-5. (pciccr; pci:09h ? 0bh) pci class code bit description read write value after reset 7:0 register level programming interface. none defined. yes only if rrc[7]=1; serial eeprom 0h 15:8 subclass code. pci-to-pci bridge or other bridge device. yes only if rrc[7]=1; serial eeprom 04h 23:16 base class code. bridge device. yes only if rrc[7]=1; serial eeprom 06h register 6-6. (pciclsr; pc i:0ch) pci cache line size bit description read write value after reset 7:0 system cache line size. specified in units of 32-bit words (dwords). only cache line sizes of a power of two are valid. maximum value is 20h. for values greater than 20h, pci 6520 operates as if pcic lsr is programmed with value of 08h. used when terminating memory write and invalidate transactions. memory read prefetching is controlled by the prefetch count registers. yes yes 0h register 6-7. (pciltr; pci:0dh) primary pci bus latency timer bit description read write value after reset 7:0 primary pci bus latency timer. specifies amount of time (in units of pci bus clocks) the pci 6520, as a bus master, can burst data on the primary pci bus. yes yes 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-7 6?registers register 6-8. (pcihtr; pci:0eh) pci header type bit description read write value after reset 6:0 configuration layout type. specifies register layout at offsets 10h to 3fh in configuration space. header type 0 is defined for pci devices ot her than pci-to-pci bridges (header type 1) and cardbus bridges (header type 2). yes only if rrc[7]=1; serial eeprom 1h 7 multi-function device. value of 1 indicates multiple (up to eight) functions (logical devices), each containing its own, individually addressable configuration space, 64 dwords in size. yes only if rrc[7]=1; serial eeprom 0 register 6-9. (pcibistr; pci:0fh) pci built-in self-test bit description read write value after reset 7:0 built-in self-test (bist). not supported. yes no 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-8 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-10. (pcipbno; pci:18h) pci primary bus number bit description read write value after reset 7:0 primary bus number. programmed with the pci and/or pci-x bus number to which the primary bridge interface is connected. yes yes 0h register 6-11. (pcisbno; pci:19h) pci secondary bus number bit description read write value after reset 7:0 secondary bus number. programmed with the pci and/or pci-x bus number to which the secondary bridge interface is connected. yes yes 0h register 6-12. (pcisubno; pci: 1ah) pci subordinate bus number bit description read write value after reset 7:0 subordinate bus number. programmed with the pci and/or pci-x bus number with the hi ghest number subordinate to the bridge. yes yes 0h register 6-13. (pcisltr; pci:1bh) secondary pci bus latency timer bit description read write value after reset 7:0 secondary pci bus latency timer. specifies the amount of time (in units of pci bus clocks) the pci 6520, as a bus master, can burst data on the secondary pci bus. yes yes 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-9 6?registers register 6-14. (pciiobar; pci:1ch) i/o base bit description read write value after reset 7:0 i/o base. specifies the i/o base address range bits [15:12] for forwarding the cycle through the bridge (base address bits [11:0] are assumed to be 0h). used in conjunction with the i/o limit, i/o base upper 16 bits, and i/o limit upper 16 bits registers (pciiolmt; pci:1dh, pciiobaru16; pci:30h, and pciiolmtu16; pci:32h, respectively) to specify a r ange of 32-bit addresses supported for pci bus i/o transactions. the lower four bits [3:0] are read-only and hardcoded to 0001b to indicate 32-bit i/o addressing support. yes yes [7:4] 1h register 6-15. (pciiolmt; pci:1dh) i/o limit bit description read write value after reset 7:0 i/o limit. specifies the upper i/o limit address range bits [15:12] for forwarding the cycle through the bridge (limit address bits [11:0] are assumed to be fffh). used in conjunction with the i/o base, i/o base upper 16 bits, and i/o limit upper 16 bits registers (pciiobar; pci:1ch, pciiobaru16; pci:30h, and pciiolmtu16; pci:32h, respectively) to specify a range of 32-bit addresses supported for pci bus i/o transactions. the lower four bits [3:0] are read-only and hardcoded to 0001b to indicate 32-bit i/o addressing support. yes yes [7:4] 1h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-10 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-16. (pcissr; pci:1eh) secondary pci status bit description read write value after reset 4:0 reserved. yes no 0h 5 66 mhz-capable. if set to 1, the pci 6520 supports a 66 mhz pci clock environment. yes no 1 6 udf. no user-definable features. yes no 0 7 fast back-to-back capable. fast back-to-back write capable on secondary port. not supported. yes no 0 8 data parity error detected. set when the following conditions are met: s_perr# is asserted, and command register parity error response enable bit is set (pcicr[6]=1; pci:04h) writing 1 clears bit to 0. yes yes/clr 0 10:9 devsel# timing . reads as 01b to indicate pci 6520 responds no slower than with medium timing. yes no 01b 11 signaled target abort. set by a target device when a target abort cycle occurs. writing 1 clears bit to 0. yes yes/clr 0 12 received target abort. set to 1 by pci 6520 when transactions are terminated with target abort. writing 1 clears bit to 0. yes yes/clr 0 13 received master abort. set to 1 by pci 6520 when transactions are terminated with master abort. writing 1 clears bit to 0. yes yes/clr 0 14 signaled system error. set when s_serr# is asserted. writing 1 clears bit to 0. yes yes/clr 0 15 parity error detected. set when a parity error is detected, regardless of the parity error response enable bit state (pcicr[6]=x]; pci:04h). writing 1 clears bit to 0. yes yes/clr 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-11 6?registers register 6-17. (pcimbar; pci:20h) memory base bit description read write value after reset 15:0 memory base. specifies the memory-mapped i/o base address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the memory limit register (pcimlmt; pci:22h) to specify a range of 32-bit addresses supported for pci bus memory-mapped i/o transactions. the lower four bits [3:0] are read-only and hardcoded to 0h. yes yes [15:4] 0h register 6-18. (pcimlmt; pci:22h) memory limit bit description read write value after reset 15:0 memory limit. specifies the upper memory-mapped i/o limit address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the memory base register (pcimbar; pci:20h) to specify a range of 32-bit addresses supported for pci bus memory-mapped i/o transactions. the lower four bits [3:0] are read-only and hardcoded to 0h. yes yes [15:4] 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-12 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-19. (pcipmbar; pci: 24h) prefetchable memory base bit description read write value after reset 15:0 prefetchable memory base. specifies the prefetchable memory-mapped base address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the prefetchable memory limit, prefetchable memory base upper 32 bits, and prefetchable memory limit upper 32 bits registers (pcipmlmt; pci:26h, pcipmbaru32; pci:28h, and pcipmlmtu32; pci:2ch, respectively) to specify a r ange of 64-bit addresses supported for prefetchable memory transactions on the pci bus. the lower four read-only bits are hardcoded to 01h, indicating 64-bit address support. yes yes [15:4] 1h register 6-20. (pcipmlmt; pci: 26h) prefetchable memory limit bit description read write value after reset 15:0 prefetchable memory limit. specifies the upper prefetchable memory-mapped limit address range bits [31:20] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the prefetchable memory base, prefetchable memory base upper 32 bits, and prefetchable memory limit upper 32 bits registers (pcipmbar; pci:24h, pcipmbaru32; pci:28h, and pcipmlmtu32; pci:2ch, respectively) to specify a r ange of 64-bit addresses supported for prefetchable memory transactions on the pci bus. the lower four read-only bits are hardcoded to 01h, indicating 64-bit address support. yes yes [15:4] 1h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-13 6?registers register 6-21. (pcipmbaru32; pci:28h) prefetchable memory base upper 32 bits bit description read write value after reset 31:0 prefetchable memory base upper 32 bits. specifies the upper prefetchable memory-mapped base address range bits [63:32] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the prefetchable memory base, prefetchable memory limit, and prefetchable memory limit upper 32 bits registers (pcipmbar; pci:24h, pcipmlmt; pci:26h, and pcipmlmtu32; pci:2ch, respectively) to specify a range of 64-bi t addresses supported for prefetchable memory transactions on the pci bus. yes yes 0h register 6-22. (pcipmlmtu32; pci:2ch) prefetchable memory limit upper 32 bits bit description read write value after reset 31:0 prefetchable memory limit upper 32 bits. specifies the upper prefetchable memory-mapped limit address range bits [63:32] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the prefetchable memory base, prefetchable memory limit, and prefetchable memory base upper 32 bits registers (pcipmbar; pci:24h, pcipmlmt; pci:26h, and pcipmbaru32; pci:28h, respectively) to specify a range of 64-bit addresses supported for prefetchable memory transactions on the pci bus. yes yes 0h register 6-23. (pciiobaru16; pci:30h) i/o base upper 16 bits bit description read write value after reset 15:0 i/o base upper 16 bits. specifies the upper i/o base address range bits [31:16] for forwarding the cycle through the bridge. base address bits [11:0] are assumed to be 0h. used in conjunction with the i/o base, i/o limit, and i/o limit upper 16 bits registers (pciiobar; pci:1ch, pciiolmt; pci:1dh, and pciiolmtu16; pci:32h, respectively) to specify a range of 32-bit addresses supported for pci bus i/o transactions. yes yes 0h register 6-24. (pciiolmtu16; pci:32h) i/o limit upper 16 bits bit description read write value after reset 15:0 i/o limit upper 16 bits. specifies the upper i/o limit address range bits [31:16] for forwarding the cycle through the bridge. limit address bits [11:0] are assumed to be fffh. used in conjunction with the i/o base, i/o limit, and i/o base upper 16 bits registers (pciiobar; pci:1ch, pciiolmt; pci:1dh, and pciiobaru16; pci:30h, respectively) to specify a range of 32-bit addres ses supported for pci bus i/o transactions. yes yes 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-14 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-25. (cap_ptr; pci:34h) new capability pointer bit description read write value after reset 7:0 new capability pointer. provides an offset into pci configuration space for the power management capability location in the new capabilities linked list. yes no dch 31:8 reserved. yes no 0h register 6-26. (pciipr; pci:3dh) pci interrupt pin bit description read write value after reset 7:0 interrupt pin. reads as 0h to indicate that pci 6520 does not use interrupt pins. yes no 0h register 6-27. (bcntrl; pci:3eh) bridge control bit description read write value after reset 0 parity error response enable. controls bridge response to parity errors on secondary interface. values: 0 = ignores address and data parity errors on secondary interface 1 = enables parity error reporting and detection on secondary interface yes yes 0 1 s_serr# enable. controls forwarding of s_serr# to primary interface. values: 0 = disables s_serr# forwarding to primary 1 = enables s_serr# forwarding to primary yes yes 0 2 isa enable. controls bridge response to isa i/o addresses, which is limited to the first 64 kb. values: 0 = forwards i/o addresses in the range defined by the i/o base and limit registers (pciiobar; pci:1ch and pciiolmt; pci:1dh, respectively). 1 = blocks forwarding of isa i/o addresses in the range defined by the i/o base and limit registers in the first 64 kb of i/o space that address the last 768 bytes in each 1-kb block. secondary i/o transactions are forwarded upstream, if the address falls within the last 768 bytes in each 1-kb block. command configuration register master enable bit must also be set (pcicr[2]=1; pci:04h) to enable isa. yes yes 0 3 vga enable. controls bridge response to vga-compatible addresses. values: 0 = does not forward vga-compatible memory nor i/o addresses from primary to secondary 1 = forwards vga-compatible memory and i/o addresses from primary to secondary, regardless of other settings note: if set to 1, then i/o addresses in the range of 3b0h to 3bbh and 3c0h to 3dfh are forwarded, regardless of the pcicr[5]; pci:04h or bcntrl[2] values. yes yes 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-15 6?registers 4 reserved. yes no 0 5 master abort mode. controls bridge behavior in response to master aborts on secondary interface. values: 0 = does not report master aborts (return ffff_ffffh on reads or discard data on writes). 1 = reports master aborts by signaling target abort. if the master abort is the result of a primary-to-secondary posted write cycle, p_serr# is asserted (pcicr[8]=1; pci:04h). note: during lock cycles, pci 6520 ignores this bit, and completes the cycle as a target abort. yes yes 0 6 secondary reset. forces s_rstout# assertion on secondary interface. values: 0 = does not force s_rstout# assertion 1 = forces s_rstout# assertion yes yes 0 7 fast back-to-back enable. controls bridge ability to generate fast back-to-back transactions to various devices on secondary interface. values: 0 = no fast back-to-back transaction 1 = reserved ; pci 6520 does not generate fast back-to-back cycles yes yes 0 8 primary master timeout (discard timer). sets the maximum number of pci clocks for an initiator on the primary bus to repeat the delayed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks yes yes 0 9 secondary master timeout (discard timer). sets the maximum number of pci clocks for an initiator on the secondary bus to repeat the delayed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks yes yes 0 10 master timeout status. set to 1 when primary or secondary master timeout occurs. writing 1 clears bit to 0. yes yes/clr 0 11 master timeout p_serr# enable. enable p_serr# assertion during master timeout. values: 0 = p_serr# not asserted on master timeout 1 = p_serr# asserted on primary or secondary master timeout yes yes 0 15:12 reserved. yes no 0h register 6-27. (bcntrl; pci:3e h) bridge control (continued) bit description read write value after reset
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-16 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2 device-specific 6.1.2.1 chip, diagnostic , and arbiter control register 6-28. (ccntrl; pci:40h) chip control bit description read write value after reset 0 reserved. yes no 0 1 memory write disconnect control. controls when pci 6520, as a target, disc onnects memory transactions. values: 0 = disconnects on queue fu ll or on a 4-kb boundary 1 = disconnects on a cache line boundary, when the queue fills, or on a 4-kb boundary yes yes 0 2 private memory enable. the memory space can be programmed using the private memory base and limit registers (pvtmbar; pci:6ch and pvtlmt; pci:6eh, respectively). if the limit is smaller than the base, the private memory space is disabled regardless of bit setting. when enabled, the primary port cannot access primary and secondary private memory s pace through the bridge and the secondary port does not respond to memory cycles addressing the private memory space. resets to the value presented on the prv_dev input pin. after reset, bit can be reprogrammed. values: 0 = disables private memory block 1 = enables private memory block yes yes prv_dev 3 private device enable. pci 6520 can re-route secondary idsels using s_ad[23:16] fo r private devices. a type 1 configuration access on the primary bus (which would normally result in the assertion of an idsel connected to s_ad[23:16]) is routed to s_ad24. if there is no device on s_ad24, the re-routed type 1 configuration cycles result in a master abort. re-routing allows s_ad[23:16] to be used for secondary private devices. resets to the value presented in the prv_dev input pin. after reset, bit can be reprogrammed. values: 0 = does not re-route idsel assertions 1 = enables the re-routing of the secondary idsel s_ad[23:16] to s_ad24 yes yes prv_dev 4 secondary bus prefetch disable. controls pci 6520 ability to prefetch during upstream memory read transactions. values: 0 = prefetches and does not fo rward byte enables during memory read transactions. 1 = requests only 1 dword from the target during memory read transactions and forwards byte enables. pci 6520 returns a target disconnect to the requesting master on the first data transfer. memory read line and memory read multiple transactions remain prefetchable. yes yes 0 7:5 reserved. yes no 000b
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-17 6?registers register 6-29. (dcntrl; pc i:41h) diagnostic control bit description read write value after reset 0 chip reset. chip and secondary bus reset. setting bit activates full chip reset, asserts s_rstout#, and forces the bridge control register secondary reset bit to be set (bcntrl[6]=1; pci:3eh). after resetting the pci 6520 registers, bit is cleared; however, bcntrl[6] remains set to 1. writing 0 has no effect. yes yes 0 2:1 reserved and must be set to 00b. yes yes 00b 3 secondary reset output mask. not supported .yesno0 7:4 reserved. yes no 0h register 6-30. (acntrl; pci:42h) arbiter control bit description read write value after reset 7:0 arbiter control. each bit controls whether a secondary bus master is assigned to the high- or low-priority group. bits correspond to request inputs s_req[7:0]#, respectively. value of 1h assigns the bus master to the high-priority group. yes yes 0h 8 reserved. yes yes 0 9 pci 6520 priority. defines whether pci 6520 secondary port is in the high- or low-priority group. 0 = low-priority group 1 = high-priority group yes yes 1 11:10 reserved. yes no 00b 12 primary port ordering rule. reserved and must be set to 0. yes yes 0 13 secondary port ordering rule . reserved and must be set to 0. yes yes 0 14 upstream 64-bit cycle control. reserved and must be set to 0. yes yes 0 15 downstream 64-bit cycle control. reserved and must be set to 0. yes yes 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-18 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.2 primary flow-through control register 6-31. (pftcr; pci:44h) primary flow-through control bit description read write value after reset 2:0 primary posted write completion wait count. maximum number of clocks the pci 6520 waits for posted write data from the initiator, if delivering write data in flow-through mode, with the internal post write queues almost empty. if the count is exceeded, without additional data from the initiator, the cycle to the target is terminated and later completed. value: 000b = de-asserts s_irdy# and waits seven clocks for data on the primary bus before terminating cycle all other values are reserved. note: to specify other clock values, use software or the serial eeprom to set these bits to any value between two and seven clocks. yes yes; serial eeprom 000b 3 reserved. yes no 0 6:4 primary delayed read completion wait count. maximum number of clocks the pci 6520 waits for delayed read data from the target if returning read data in flow-through mode, and the internal delayed read queue is almost full. if the count is exceeded without additional space in the queue, the cycle to the target is terminated, and completed when the initiator retries the remainder of the cycle. value: 000b = de-asserts s_irdy# and waits seven clocks for further data to be transferred to the primary bus before terminating cycle all other values are reserved. note: to specify other clock values, use software or the serial eeprom to set these bits to any value between two and seven clocks. yes yes; serial eeprom 000b 7 reserved. yes no 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-19 6?registers 6.1.2.3 timeout control register 6-32. (tocntrl; pci:45h) timeout control bit description read write value after reset 2:0 maximum retry counter control. controls the maximum number of times the pci 6520 retries a cycle before signaling a timeout. timeout applies to read/write retries and can be enabled to trigger serr# on the primary or secondary port, depending on the serr# events enabled. maximum number of retries to timeout: 000b = 2 24 001b = 2 18 010b = 2 12 011b = 2 6 111b = 2 0 yes yes; serial eeprom 000b 3 reserved. yes no 0 5:4 primary master timeout divider. provides additional options for the primary master timeout. in addition to its original setting in the bridge control register (bcntrl[8]; pci:3eh), the timeout counter can optionally be divided by up to 256: 00b = counter?primary master timeout / 1 01b = timeout counter?primary master timeout / 8 10b = timeout counter?primary master timeout / 16 11b = timeout counter?primary master timeout / 256 bcntrl[8] can set the primary master timeout to 32k (default) or 1k clock cycles. yes yes; serial eeprom 00b 7:6 secondary master timeout divider. provides additional options for the secondary master timeout. in addition to its original setting in the bridge control register (bcntrl[9]; pci:3eh), the timeout counter can optionally be divided by up to 256: 00b = counter?secondary master timeout / 1 01b = timeout counter?secondary master timeout / 8 10b = timeout counter?secondary master timeout / 16 11b = timeout counter?secondary master timeout / 256 bcntrl[9] can set the secondary master timeout to 32k (default) or 1k clock cycles. yes yes; serial eeprom 00b
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-20 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.4 miscellaneous options register 6-33. (mscopt; pci:46h) miscellaneous options bit description read write value after reset 0 write completion wait for perr#. if set to 1, pci 6520 waits for target perr# status before completing a delayed write transaction to the initiator. yes yes; serial eeprom 0 1 read completion wait for par. if set to 1, pci 6520 waits for target par status before completing a delayed read transaction to the initiator. yes yes; serial eeprom 0 2 drt out-of-order enable. if set to 1, pci 6520 may return delayed read transactions in a different order than requested. otherwise, dela yed read transactions are returned in the same order as requested. yes yes; serial eeprom 0 3 generate parity enable. values: 0 = passes along the cycle par/par64, as stored in the internal buffers 1 = pci 6520, as a master, generates par/par64 to cycles traveling across the bridge yes yes; serial eeprom 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-21 6?registers 6:4 address step control. during type 0 configuration cycles, pci 6520 drives the address for the number of clocks specified by these bits, before asserting frame#. defaults to 001b in conventional pci mode. in pci-x mode, these bits have no effect and address stepping is hardcoded to four clocks. values: 000b = concurrently asserts fr ame# and drives the address on the bus 001b = asserts frame# one clock after driving the address on the bus ? 111b = asserts frame# seven clocks after driving the address on the bus yes yes; serial eeprom 001b 8:7 reserved. yes no 00b 9 prefetch early termination. values: 0 = terminates prefetching at the initial prefetch count if flow through is not achieved, and another prefetching read cycle is accepted by the pci 6520 1 = completes prefetching as programmed by the prefetch count registers, regardless of other outstanding prefetchable reads in the transaction queue yes yes; serial eeprom 0 10 read minimum enable. if set to 1, pci 6520 only initiates read cycles if there is sufficient space available in the fifo as required by the prefetch count registers. yes yes; serial eeprom 0 15, 11 force 64-bit control. if set and the target supports 64-bit transfers, 32-bit prefetchable reads or 32-bit posted memory write cycles on one side are c onverted to 64-bit cycles on completion at the target bus. if set to 00b, cycles are not converted. values: 00b = disable (default) 01b = convert to 64-bit command on both ports 10b = convert to 64-bit command on secondary port 11b = convert to 64-bit command on primary port yes yes; serial eeprom 0 12 memory write and invalidate control. values: 0 = retries memory write and invalidate commands if there is insufficient space for one cache line of data in the internal queues. 1 = passes memory write and invalidate commands if there are one or more cache lines of fifo space available. if there is insufficient space, completes as a memory write cycle. yes yes; serial eeprom 0 13 primary lock enable. if set to 1, pci 6520 follows the lock protocol on primary interface; otherwise, lock is ignored. yes yes; serial eeprom 0 14 secondary lock enable. if set to 1, pci 6520 follows the lock protocol on secondary in terface; otherwise, lock is ignored. yes yes; serial eeprom 0 register 6-33. (mscopt; pci:46h) miscellaneous options (continued) bit description read write value after reset
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-22 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.5 prefetch control registers 48h to 4eh are the flow-through prefetch control registers, which are used to fine-tune the pci 6520 memory read prefetch behavior. (refer to section 18, ?pci flow-through optimization,? for further details regarding these registers.) these registers apply only if there are one or more ports operating in conventional pci mode. register 6-34. (pitlpcnt; pci:48h ) primary initial prefetch count bit description read write value after reset 0 reserved. yes no 0 2:1 pci-x primary initial prefetch count. when the primary bus is in pci-x mode, these bits control the initial prefetch count on the primary bus during reads to prefetchable memory space. value defines the cache line multiples for the initial prefetch count. prefetch as follows: 00b = 1 cache line (size defined by pciclsr; pci:0ch) 01b = 2 cache lines 10b = 4 cache lines 11b = 8 cache lines the primary pci-x 16 cache line prefetch bit (pincpcnt[1]; pci:4ah) enables prefetch of 16 cache lines. yes yes; serial eeprom 00b 5:3 pci primary initial prefetch count. when the primary bus is in conventional pci mode, controls the initial prefetch count on the primary bus during reads to prefetchable memory space. prefetch as follows: 001b = 08h dwords 010b = 10h dwords 101b = 20h dwords other values are reserved . yes yes; serial eeprom 001b 7:6 reserved. yes no 00b
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-23 6?registers register 6-35. (sitlpcnt; pci:49h) secondary initial prefetch count bit description read write value after reset 0 reserved. yes no 0 2:1 pci-x secondary initial prefetch count. when the secondary bus is in pci-x mode, these bits control the initial prefetch count on the secondary bus during reads initiated from the primary port. value defines the cache line multiples for the initial prefetch count. prefetch as follows: 00b = 1 cache line (size defined by pciclsr; pci:0ch) 01b = 2 cache lines 10b = 4 cache lines 11b = 8 cache lines the secondary pci-x 16 cache line prefetch bit (sincpcnt[1]; pci:4bh) enables prefetch of 16 cache lines. yes yes; serial eeprom 00b 5:3 pci secondary initial prefetch count. when the secondary bus is in conventional pci mode, these bits control the initial prefetch count on the secondary bus during reads initiated from the primary port. prefetch as follows: 001b = 08h dwords 010b = 10h dwords 101b = 20h dwords other values are reserved . yes yes; serial eeprom 001b 6 primary write flush enable. values: 0 = downstream writes (any type) do not affect smart prefetch entries 1 = flushes all active smart pr efetch entries on downstream writes yes yes; serial eeprom 0 7 secondary write flush enable. values: 0 = upstream memory writes do not affect smart prefetch entries 1 = flushes the entry if t he upstream write address hits 4-kb page of the smart prefetch entries yes yes; serial eeprom 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-24 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-36. (pincpcnt; pci:4ah) primary incremen tal prefetch count bit description read write value after reset 0 reserved. yes no 0 1 primary pci-x 16 cache line prefetch. value: 1 = enables primary pci-x port to prefetch 16 cache lines. when set, the pci-x primary initial prefetch count bits are ignored (pitlpcnt[2:1]; pci:48h). yes yes; serial eeprom 0 5:2 primary incremental prefetch count. applies only to primary port conventio nal pci mode operation. these bits control the incremental read prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge prefetches additional primary incremental prefetch count dwords. value is specified as a multiple of 4 x dwords. the register value must not exceed half the value programmed in the primary maximum prefetch count register (pmaxpcnt; pci:4ch); otherwise, no incremental prefetch is performed. prefetch as follows: 0000b = no incremental prefetch 0001b = 04h dwords 0010b = 08h dwords 0011b = 0ch dwords ? 1111b = 3ch dwords yes yes; serial eeprom 0000b 7:6 reserved. yes no 00b register 6-37. (sincpcnt; pci:4bh) secondary incremental prefetch count bit description read write value after reset 0 reserved. yes no 0 1 secondary pci-x 16 cache line prefetch. value: 1 = enables secondary pci-x port to prefetch 16 cache lines. when set, the pci-x secondary initial prefetch count bits are ignored (sitlpcnt[2:1]; pci:49h). yes yes; serial eeprom 0 5:2 secondary incremental prefetch count. applies only to secondary port conventional pci mode operation. these bits control the incremental read prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge prefetches additional secondary incremental prefetch count dwords. value is specified as a multiple of 4 x dwords. the register value must not exceed half the value programmed in the secondary maximum prefetch count register (smaxpcnt; pci:4dh); otherwise, no incremental prefetch is performed. prefetch as follows: 0000b = no incremental prefetch 0001b = 04h dwords 0010b = 08h dwords 0011b = 0ch dwords ? 1111b = 3ch dwords yes yes; serial eeprom 0000b 7:6 reserved. yes no 00b
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-25 6?registers register 6-38. (pmaxpcnt; pci:4ch) primary maximum prefetch count bit description read write value after reset 5:0 primary maximum prefetch count. applies only to pci-to-pci bridging. limits the cumulative maximum count of prefetchable dwords allocated to one entry on the primary bus when flow through for that entry is not achieved. value should be an even number. bit 0 is read-only and always 0. value is specified in dwords, except if 0 value is programmed, which sets the primary maximum prefetch count to its maximum value of 256 bytes. a pci read cycle causes a pci request for the maximum count data. yes yes [5:1]; serial eeprom 20h 7:6 reserved. yes no 00b register 6-39. (smaxpcnt; pci:4dh) secondary maximum prefetch count bit description read write value after reset 5:0 secondary maximum prefetch count. applies only to pci-to-pci bridging. limits the cumulative maximum count of prefetchable dwords allocated to one entry on the secondary bus when flow through for that entry is not achieved. value should be an even number. bit 0 is read-only and always 0. value is specified in dwords, except if 0 value is programmed, which sets the secondary maximum prefetch count to its maximum value of 256 bytes. a pci read cycle causes a pci request for the maximum count data. yes yes [5:1]; serial eeprom 20h 7:6 reserved. yes no 00b
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-26 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.6 secondary flow-through control register 6-40. (sftcr; pci:4eh) secondary flow-through control bit description read write value after reset 2:0 secondary posted write completion wait count. maximum number of clocks the pci 6520 waits for posted write data from the initiator if delivering write data in flow-through mode and the internal post write queues are almost empty. if the count is exceeded without additional data from the initiator, the cycle to the target is terminated and later completed. value: 000b = de-asserts p_irdy# and waits seven clocks for data on the secondary bus, before terminating cycle all other values are reserved. note: to specify other clock values, use software or the serial eeprom to set these bits to any value between two and seven clocks. yes yes; serial eeprom 000b 3 reserved. yes no 0 6:4 secondary delayed read completion wait count. maximum number of clocks the pci 6520 waits for delayed read data from the target, if returning read data in flow-through mode and the internal delayed read queue is almost full. if the count is exceeded without additional space in the queue, the cycle to target is terminated, and completed when initiator retries the remainder of the cycle. value: 000b = de-asserts p_irdy# and waits seven clocks for additional space to be transferred to the secondary bus before terminating cycle all other values are reserved. note: to specify other clock values, use software or the serial eeprom to set these bits to any value between two and seven clocks. yes yes; serial eeprom 000b 7 reserved. yes no 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-27 6?registers 6.1.2.7 buffer and internal arbiter control register 6-41. (bufcr; pci:4fh) buffer control bit description read write value after reset 0 reserved. yes no 0 1 smart prefetch enable. the amount of data prefetched is defined in the maximum prefetch count registers (pmaxpcnt; pci:4ch and smaxpcnt; pci:4dh). values after a prefetch command: 0 = remaining prefetched data is discarded upon completion of the current read command. 1 = remaining prefetched data is not discarded, but remains available for the next read command with consecutive address. the prefetched data is only discarded upon a timeout. the timeout period can be programmed using the smart prefetch timeout bits (bufcr[6:5]; pci:4fh). yes yes 0 2 split fifo enable. buffer split for individual data entries. values: 0 = entire fifo shared among entries and the fifo is undedicated 1 = fifo divided into four equal parts, to be dedicated to each entry for split completions yes yes 0 4:3 reserved. yes no 00b 6:5 smart prefetch timeout. smart prefetch timeout affects only pci-to-pci, pci-to-pci-x, or pci-x-to-pci bridging applications. prefetches cannot cross the 4-kb address boundary. when smart prefetch is enabled, the prefetched data is only discarded upon a timeout. the timeout periods available are after: 00b = 32 pci clocks 01b = 64 pci clocks 10b = 128 pci clocks 11b = 256 pci clocks yes yes 11b 7 reserved. yes no 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-28 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-42. (iacntrl; pci:50h) internal arbiter control bit description read write value after reset 0 low-priority group fixed arbitration. if set to 1, the low-priority group uses fixed-pr iority arbitration; otherwise, rotating-priority arbitration is used. yes yes 0 1 low-priority group arbitration order. valid only when the low-priority arbitration group is set to a fixed arbitration scheme. values: 0 = priority decreases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 3 retains higher priority than master 4.) 1 = priority increases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 4 retains higher priority than master 3. this order is relative to the master with the highest priority for this group, as specified in iacntrl[7:4]. yes yes 0 2 high-priority group fixed arbitration. if set to 1, the high-priority group uses the fi xed-priority arbitration; otherwise, rotating-prior ity arbitration is used . yes yes 0 3 high-priority group arbitration order. valid only when the high-priority arbitration group is set to a fixed arbitration scheme. values: 0 = priority decreases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 3 retains higher priority than master 4.) 1 = priority increases with bus master number. ( for example, assuming master 2 is set as the highest priority master, master 4 retains higher priority than master 3.) this order is relative to the master with the highest priority for this group, as specified in iacntrl[11:8]. yes yes 0 7:4 highest priority master in low-priority group. controls which master in the low-priority group retain the highest priority. valid only if the group uses the fixed arbitration scheme. values: 0000b = master 0 retains highest priority 0001b = master 1 retains highest priority ? 1000b = pci 6520 retains highest priority 1001b ? 1111b = reserved yes yes 0000b 11:8 highest priority master in high-priority group. controls which master in the high-priority group retains the highest priority. valid only if the group uses the fixed arbitration scheme. values: 0000b = master 0 retains highest priority 0001b = master 1 retains highest priority ? 1000b = pci 6520 retains highest priority 1001b ? 1111b = reserved yes yes 0000b 15:12 bus grant parking control. controls bus grant behavior during idle. value: 0h = indicates the last master granted is parked all other values are reserved. yes no 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-29 6?registers 6.1.2.8 test and serial eeprom register 6-43. (test; pci:52h) test bit description read write value after reset 0 serial eeprom autoload control. if set to 1, disables serial eeprom autoload. yes yes 0 1 fast serial eeprom autoload. if set to 1, speeds up serial eeprom autoload. yes yes 0 2 serial eeprom autoload status. serial eeprom autoload status is set to 1 during autoload. yes no status of serial eeprom autoload 3 s_pll_test. when p_clkoe input pin is set to 1 and this bit is set to 1, s_clko4 (derived from s_clkin) is divided by 4. yes yes 0 4 dev64#. reflects dev64# pin status. yes no dev64# 5 s_cfn#. reflects s_cfn# pin status. yes no s_cfn# 7:6 reserved. returns 0 when read. yes no 00b register 6-44. (eepcntrl; pci:54h) serial eeprom control bit description read write value after reset 0 start. starts serial eeprom read or write cycle. bit is cleared when serial eeprom load completes. yes yes 0 1 serial eeprom command. controls commands sent to the serial eeprom. values: 0 = read 1 = write yes yes 0 2 serial eeprom error. set to 1 if serial eeprom ack was not received during serial eeprom cycle. yes no ? 3 serial eeprom autoload successful. set to 1 if serial eeprom autoload successfully occurred after reset, with appropriate configuration registers loaded with the values programmed in the serial eeprom. if 0, the serial eeprom autoload was unsuccessful or disabled. yes no ? 5:4 reserved. returns 00b when read. yes no 00b 7:6 serial eeprom clock rate. controls the serial eeprom clock frequency. the serial eeprom clock is derived from the primary pci clock. values: 00b = pclk / 2048 01b = pclk / 1024 10b = pclk / 256 11b = pclk / 32 yes yes 01b
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-30 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-45. (eepaddr; pci:55h) serial eeprom address bit description read write value after reset 0 reserved . yes no ? 7:1 serial eeprom address. word address for the serial eeprom cycle. yes yes ? register 6-46. (eepdata; pci:56h) serial eeprom data bit description read write value after reset 15:0 serial eeprom data. contains data to be written to the serial eeprom. during reads, contains data received from the serial eeprom after a read cycle completes. yes yes ?
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-31 6?registers 6.1.2.9 timer register 6-47. (tmrcntrl; pci:61h) timer control bit description read write value after reset 0 timer enable. set to start measurement of the approximate bus frequency on the primary or secondary interface. by default, bit is 0, and must be set to 1 to start the measurement. when set to 0 and then to 1, pci 6520 starts counting up until it reaches the set count period. during this counting period, pci 6520 timer counter (tmrcnt; pci:62h) counts the number of timer counter clocks. yes yes 0 2:1 timer counter clock source select. values: 00b = primary pci clock (p_clkin) 01b = secondary pci clock (s_clkin) 10b, 11b = reserved yes yes 00b 3 timer stop. timer stopped status bit. when the measurement is finished, this bit is set to 0, and then to 1. when starting a new measurement , this bit automatically restores to 0. values: 0 = timer running 1 = timer stopped yes no 0 5:4 count period. values: 00b = 16 reference clock high states 01b = 32 reference clock high states 10b = 64 reference clock high states 11b = 128 reference clock high states yes yes 00b 7:6 reserved. yes no 00b register 6-48. (tmrcnt; pci:62h) timer counter bit description read write value after reset 15:0 timer counter. automatically stops upon the count period setting in the timer control register (tmrcntrl[7:4]; pci:61h). this counter can be enabled by setting the timer enable bit (tmrcntrl[0]; pci:61h) first to 0, and then to 1. yes no 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-32 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.10 primary system error event register 6-49. (pserred; pci:64h) p_serr# event disable bit description read write value after reset 0 reserved. yes no 0 1 posted write parity error. controls pci 6520 ability to assert p_serr# when a data parity error is detected on the target bus during a posted write transaction. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 2 posted memory write non-delivery. controls pci 6520 ability to assert p_serr# when it is unable to deliver posted write data after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 3 target abort during posted write. controls pci 6520 ability to assert p_serr# when it receives a target abort while attempting to deliver posted write data. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 4 master abort on posted write. controls pci 6520 ability to assert p_serr# when it receives a master abort while attempting to deliver posted write data. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 5 delayed configuration or i/o write non-delivery. controls pci 6520 ability to assert p_serr# when it is unable to deliver delayed write data after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 6 delayed read-no data from target. controls pci 6520 ability to assert p_serr# when it is unable to transfer read data from the target after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 7 reserved. returns 0 when read. yes no 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-33 6?registers 6.1.2.11 gpio[3:0] register 6-50. (gpiood[3:0]; pci:65h) gpio[3:0] output data bit description read write value after reset 3:0 gpio[3:0] output data write 1 to clear. writing 1 to these bits drives the corresponding signal low on the gpio[3:0] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/clr 0h 7:4 gpio[3:0] output data write 1 to set. writing 1 to these bits drives the corresponding signal high on the gpio[3:0] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-51. (gpiooe[3:0]; pci:66h) gpio[3:0] output enable bit description read write value after reset 3:0 gpio[3:0] output enable write 1 to clear. writing 1 to these bits configures the corresponding signal on the gpio[3:0] bus as an input. writing 0 has no effect. read returns last written value. yes yes/clr 0h 7:4 gpio[3:0] output enable write 1 to set. writing 1 to these bits configures the corresponding signal on the gpio[3:0] bus as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-52. (gpioid[3:0]; pci:67h) gpio[3:0] input data bit description read write value after reset 3:0 reserved. yes no 0h 7:4 gpio[3:0] input data. reads the gpio[3:0] pin state. the state is updated on the primary pci clock cycle, following a change in gpio[3:0] state. yes no ?
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-34 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.12 clock control register 6-53. (clkcntrl; pci:68h) clock control bit description read write value after reset 1:0 clock 0 disable . if either bit is 0, s_clko0 is enabled. when both bits are 1, s_clko0 is disabled. defaults to 00b if msk_in=1. yes yes 00b 3:2 clock 1 disable. if either bit is 0, s_clko1 is enabled. when both bits are 1, s_clko1 is disabled. yes yes 00b 5:4 clock 2 disable. if either bit is 0, s_clko2 is enabled. when both bits are 1, s_clko2 is disabled. yes yes 00b 7:6 clock 3 disable. if either bit is 0, s_clko3 is enabled. when both bits are 1, s_clko3 is disabled. yes yes 00b 8 clock 4 disable. if 0, s_clko4 is enabled. when 1, s_clko4 is disabled. yes yes 0 15:9 reserved. yes no 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-35 6?registers 6.1.2.13 primary system error status register 6-54. (pserrsr; pci:6ah) p_serr# status bit description read write value after reset 0 address parity error. p_serr# is asserted because an address parity error occurred on either side of the bridge. yes yes/clr 0 1 posted write data parity error. p_serr# is asserted because a posted write data parity error occurred on the target bus. yes yes/clr 0 2 posted write non-delivery. p_serr# is asserted because pci 6520 was unable to deliver posted write data to the target before the timeout counter expired. yes yes/clr 0 3 target abort during posted write. p_serr# is asserted because pci 6520 received a tar get abort when delivering posted write data. yes yes/clr 0 4 master abort during posted write. p_serr# is asserted because pci 6520 received a mast er abort when delivering posted write data. yes yes/clr 0 5 delayed write non-delivery. p_serr# is asserted because pci 6520 was unable to deliver delayed write data before the timeout counter expired. yes yes/clr 0 6 delayed read failed. p_serr# is asserted because pci 6520 was unable to read data from the target before the timeout counter expired. yes yes/clr 0 7 delayed transaction master timeout. p_serr# is asserted because a master did not repeat a read or write transaction before the initiator bus master timeout counter expired. yes yes/clr 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-36 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.14 clock run register 6-55. (clkrun; pci:6bh) clock run bit description read write value after reset 0 secondary clock stop status. values: 0 = secondary clock not stopped 1 = secondary clock stopped yes yes 0 1 s_clkrun# enable. controls the s_clkrun# pin. values: 0 = disables s_clkrun# pin 1 = enables s_clkrun# pin yes yes 0 2 primary clock stop. values: 0 = allows primary clock to stop, if secondary clock is stopped 1 = keeps primary clock running yes yes 0 3 p_clkrun# enable. controls the p_clkrun# pin. values: 0 = disables p_clkrun# pin 1 = enables p_clkrun# pin yes yes 0 4 clkrun mode. values: 0 = stops the secondary clock only on request from the primary bus 1 = stops the secondary clock when the secondary bus is idle and there are no requests from the primary bus yes yes 0 7:5 reserved. yes no 000b
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-37 6?registers 6.1.2.15 private memory private memory can be enabled by way of the chip control register (ccntrl[2]; pci:40h) or by using the prv_dev input pin. register 6-56. (pvtmbar; pc i:6ch) private memory base bit description read write value after reset 15:0 private memory base. defines the private memory address range base address. the upper 12 bits corresponding to address bits [31:20] are writable and reset to 0h. the lower 20 address bits [19:0] are assumed to be 0h. the lower four bits are read-only and set to 0001b. yes yes [15:4] 1h register 6-57. (pvtmlmt; pci:6eh) private memory limit bit description read write value after reset 15:0 private memory limit. defines the private memory address range upper limit address. the upper 12 bits corresponding to address bits [31:20] are writable and reset to 0h. the lower 20 address bits [19:0] are assumed to be f_ffffh. the lower four bits are read-only and set to 0h. yes yes [15:4] 0h register 6-58. (pvtmbaru32; pci:70h ) private memory base upper 32 bits bit description read write value after reset 31:0 private memory base upper 32 bits . defines the upper 32-bit (bits [63:32]) memory base address of the private memory address range. note: private memory base default value is higher than the private memory limit, and ensures that the private memory space is disabled by default. yes yes 1h register 6-59. (pvtmlmtu32; pci:74h ) private memory limit upper 32 bits bit description read write value after reset 31:0 private memory limit upper 32 bits. defines the upper 32-bit (bits [63:32]) memory limit address of the private memory address range. yes yes 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-38 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.16 read-only register control register 6-60. (rrc; pci:9ch) read-only register control bit description read write value after reset 0 reserved. yes no 0 1 primary port 64-bit extension signals park. value: 1 = drives primary port pci 64-bit extension signals p_ad[63:32], p_cbe[7:4]#, and p_par64 to 0 yes yes 0 2 secondary port 64-bit extension signals park. value: 1 = drives secondary port pc i 64-bit extension signals s_ad[63:32], s_cbe[7:4]#, and s_par64 to 0 yes yes 0 6:3 reserved. must be 0h. yes no 0h 7 read-only registers write enable. setting this bit to 1 enables writes to specific bits within these normally read-only registers (refer to the listed registers for further details): vendor and device ids (pciidr; pci:00h) pci class code (pciccr; pci:09h ? 0bh) pci header type (pcihtr; pci:0eh) power management capabilities (pmc; pci:deh) power management control/status (pmcsr; pci:e0h) power management data (pmcdata; pci:e3h) bit must be cleared after the values are modified in these read-only registers. yes yes 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-39 6?registers 6.1.2.17 gpio[7:4] register 6-61. (gpiood[7:4]; pci:9dh) gpio[7:4] output data bit description read write value after reset 3:0 gpio[7:4] output data write 1 to clear. writing 1 to these bits drives the corresponding signal low on the gpio[7:4] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/clr 0h 7:4 gpio[7:4] output data write 1 to set. writing 1 to these bits drives the corresponding signal high on the gpio[7:4] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-62. (gpiooe[7:4]; pci:9eh) gpio[7:4] output enable bit description read write value after reset 3:0 gpio[7:4] output enable write 1 to clear. writing 1 to these bits configures the corresponding signal on the gpio[7:4] bus as an input. writing 0 has no effect. read returns last written value. yes yes/clr 0h 7:4 gpio[7:4] output enable write 1 to set. writing 1 to these bits configures the corresponding signal on the gpio[7:4] bus as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-63. (gpioid[7:4]; pci:9fh) gpio[7:4] input data bit description read write value after reset 3:0 reserved. yes no 0h 7:4 gpio[7:4] input data. reads the gpio[7:4] pin state. the state is updated on the primary pci clock cycle following a change in gpio[7:4] state. yes no ?
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-40 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.18 extended and smart prefetch the extended registers are accessed by way of the extended register index and data registers (extridx; pci:d3h and extrdata; pci:d4h, respectively). there are six 32-bit upstream smart prefetch bars (ext:10h to 15h) and four 32-bit upstream smart prefetch descriptor registers (ext:16h to 19h). (refer to table 6-2.) smart prefetch is enabled by way of the buffer control register (bufcr[1]=1; pci:4fh). the secondary bus upstream smart prefetch memory space is divided into four regions. regions 1, 2, and 3 (smart prefetchable) are actively decoded. region 4 (non- smart prefetchable) is the region exclusive of regions 1, 2, and 3 that are decoded by the pci 6520, where the cycles are passed upstream to the host. the three actively decoded smart prefetch regions require a 64- bit bar type register for address allocation. the smart prefetch region window size is defined in each region?s descriptor register. after one of the smart prefetchable regions (1, 2, or 3) is enabled, region 4 is enabled with the default setting, even though bit 31 of the region 4 descriptor register is set to 0. (refer to figure 6-1.) the initiated smart prefetch cycle does not prefetch data across the 4-kb boundary. all regions monitor the upstream write cycles. if a write cycle occurs in one of the smart prefetched 4-kb data pages, the write cycle causes that entry to be flushed. the smart prefetch bar registers for regions 1, 2, and 3 are located in extended configuration register space. the extended registers can be accessed by writing the 8-bit offset to the extended register index register (extridx; pci:d3h), then read or write the 32-bit data from or to the extended register data register (extrdata; pci:d4h). each smart prefetch region has one 8-bit descriptor register to define that region?s configuration. (refer to table 6-2 on page 6-41 and the registers that follow.) figure 6-1. sample memory map of smart pr efetch upstream memory, regions 1 through 4 0000_0000_0000_0000h ffff_ffff_ffff_ffffh upstream smart prefetchable regions 1, 2, and 3 downstream memory region defined in pci:20h to 2fh primary bus secondary bus downstream downstream upstream upstream upstream non-smart prefetchable region 4
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-41 6?registers note: refer to the individual register descriptions to determine which bits are writable. register 6-64. (extridx; pci:d3h) extended register index bit description read write value after reset 7:0 extended index address. index address for extended registers. yes yes ? register 6-65. (extrdata; pci:d4h) extended register data bit description read write value after reset 31:0 extended register data. configuration write causes the data presented at this port to be written into the register addressed by the extended register index (extridx; pci:d3h). configuration read causes the data from the register addressed by the extended register index to be placed into and read from extrdata. yes yes ? table 6-2. extended register map?offset from extended register index extended register index writable serial eeprom writable 31 24 23 16 15 8 70 10h region 1 upstream lower 32-bit smart prefetch bar yes no 11h region 1 upstream upper 32-bit smart prefetch bar yes no 12h region 2 upstream lower 32-bit smart prefetch bar yes no 13h region 2 upstream upper 32-bit smart prefetch bar yes no 14h region 3 upstream lower 32-bit smart prefetch bar yes no 15h region 3 upstream upper 32-bit smart prefetch bar yes no 16h region 1 upstream smart prefetch bar descriptor yes no 17h region 2 upstream smart prefetch bar descriptor yes no 18h region 3 upstream smart prefetch bar descriptor yes no 19h region 4 upstream smart prefetch bar descriptor yes no register 6-66. (spul32bar1; ext:10h) region 1 upstream lower 32-bit smart prefetch bar bit description read write value after reset 19:0 reserved. 1 mb memory address boundary resolution. must be 0. yes yes 0h 31:20 region 1 upstream lower 32-bit address for ad[31:0] of base address. yes yes 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-42 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-67. (spuu32bar1; ext:11h) region 1 upstream lower 32-bit smart prefetch bar bit description read write value after reset 31:0 region 1 upstream upper 32-bit address for ad[63:32] of base address. yes yes 0h register 6-68. (spul32bar2; ext:12h) region 2 upstream lower 32-bit smart prefetch bar bit description read write value after reset 19:0 reserved. 1 mb memory address boundary resolution. must be 0. yes yes 0h 31:20 region 2 upstream lower 32-bit address for ad[31:0] of base address. yes yes 0h register 6-69. (spuu32bar2; ext:13h) region 2 upstream lower 32-bit smart prefetch bar bit description read write value after reset 31:0 region 2 upstream upper 32-bit address for ad[63:32] of base address. yes yes 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-43 6?registers register 6-70. (spul32bar3; ext:14h) region 3 upstream lower 32-bit smart prefetch bar bit description read write value after reset 19:0 reserved. 1 mb memory address boundary resolution. must be 0. yes yes 0h 31:20 region 3 upstream lower 32-bit address for ad[31:0] of base address. yes yes 0h register 6-71. (spuu32bar3; ext:15h) region 3 upstream lower 32-bit smart prefetch bar bit description read write value after reset 31:0 region 1 upstream upper 32-bit address for ad[63:32] of base address. yes yes 0h register 6-72. (spubard x ; ext:16h?19h) regions 1?4 upstream smart prefetch bar descriptors bit description read write value after reset 1:0 smart prefetch discard timer. counting begins at end of initiator access. values: 00b = 32 clocks 01b = 64 clocks 10b = 128 clocks 11b = 256 clocks yes yes 00b 4:2 reserved. must be set to 0. yes no 000b 5 memr command flow-through enable. values: 0 = disables memr flow through, prefetches only up to initial count (default) 1 = enables memr flow through, prefetches up to the initial count, then continues to read until initiator disconnects yes yes 0 8:6 memr command prefetch count multiplier. values: 000b = prefetches until end of boundary of one cache line block (default) 001b = prefetches until end of boundary of two cache line blocks 010b = prefetches until end of boundary of four cache line blocks 011b = prefetches until end of boundary of 8 cache line blocks 100b = prefetches until end of boundary of 16 cache line blocks 101b, 110b, and 111b = reserved yes yes 000b 9 memrl command flow-through enable. values: 0 = disables memrl flow through, prefetches only up to initial count (default) 1 = enables memrl flow through, prefetches up to the initial count, then continues to read until initiator disconnects yes yes 0
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-44 preliminary ? 2004 plx technology, inc. all rights reserved. 12:10 memrl command prefetch count multiplier. values: 000b = prefetches until end of boundary of one cache line block (default) 001b = prefetches until end of boundary of two cache line blocks 010b = prefetches until end of boundary of four cache line blocks 011b = prefetches until end of boundary of 8 cache line blocks 100b = prefetches until end of boundary of 16 cache line blocks 101b, 110b, and 111b = reserved yes yes 000b 13 memrm command flow-through enable. values: 0 = disables memrm flow through, prefetches only up to initial count 1 = enables memrm flow through, prefetches up to the initial count, then continues to read until initiator disconnects (default) yes yes 1 16:14 memrm command prefetch count multiplier. values: 000b = prefetches until end of boundary of one cache line block 001b = prefetches until end of boundary of two cache line blocks (default) 010b = prefetches until end of boundary of four cache line blocks 011b = prefetches until end of boundary of 8 cache line blocks 100b = prefetches until end of boundary of 16 cache line blocks 101b, 110b, and 111b = reserved yes yes 000b 17 smart prefetch enable. values: 0 = releases entry after initiator completes its cycle (default, no smart prefetch function). 1 = retains entry if data remains after initiator completes its cycle. data is released if one of the following conditions is met: discard timer expires (spubard x [1:0]) upon upstream write, if the secondary initial prefetch count primary write flush enable bit is set (sitlpcnt[6]=1; pci:49h) upon upstream write within 4-kb page of the smart prefetch region if the secondary initial prefetch count secondary write flush enable bit is set (sitlpcnt[7]=1; pci:49h) yes yes 0 19:18 smart prefetch region cache line size. values: 00b = 8 dwords (default) 01b = 16 dwords 10b = 32 dwords 11b = 64 dwords yes yes 00b register 6-72. (spubard x ; ext:16h?19h) regions 1?4 upstream smart prefetch bar descriptors (continued) bit description read write value after reset
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-45 6?registers note: the ?x? in spubardx represents the region numbers, 1 through 4 (that is, spubard1 is the register for region 1, spubard2 is the register for region 2, and so forth). 20 smart prefetch region cache line size select. values: 0 = uses cache line size register value (pciclsr; pci:0ch) (default) 1 = uses cache line size defined in spubard x [19:18] yes yes 0 23:21 region 1, 2, and 3 smart prefetch bar window size. values: 000b = 1 mb window (default) 001b = 2 mb window 010b = 4 mb window 011b = 8 mb window 100b = 64 mb window 101b = 128 mb window 110b = 256 mb window 111b = 512 mb window yes yes 000b 25:24 prefetch disconnect policy. values: 00b = stops prefetching on the earliest of an initiator or target termination (default) 01b = ignores initiator termination, then prefetches until requested count is fulfilled, unless target prematurely disconnects 10b = reserved 11b = ignores initiator termination, then prefetches until requested count is fulfilled yes yes 00b 30:26 reserved. must be set to 0. yes no 0h 31 smart prefetch bar region enable. values: 0 = disables smart prefetch bar regions 1, 2, and 3 (default) 1 = enables smart prefetch bar regions 1, 2, and 3 note: region 4 is automatically enabled (although value is 0) when region 1, 2, and/or 3 is enabled. yes yes 0 register 6-72. (spubard x ; ext:16h?19h) regions 1?4 upstream smart prefetch bar descriptors (continued) bit description read write value after reset
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-46 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.19 power mana gement capability specific bits in the pmc; pci:deh, pmcdata; pci:e3h, and pmcsr; pci:e0h power management registers are normally read-only. however, their default values can be changed by firmware or software by setting the read-only registers write enable bit (rrc[7]=1; pci:9ch). after modifying these registers, the write enable bit must be cleared to preserve the read-only nature of these registers. it should be noted that the rrc[7] state does not affect write accesses to pmcsr[15, 8] . register 6-73. (pmcapid; pci:dch) power management capability id bit description read write value after reset 7:0 power management capability id. pci-sig-issued capability id for power management is 1h. yes no 1h register 6-74. (pmnext; pci:ddh) powe r management next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for the vpd capability location in the new capabilities linked list. yes no e8h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-47 6?registers register 6-75. (pmc; pci:deh) power management capabilities bit description read write value after reset 2:0 version. set to 001b, indicates that this function complies with pci power mgmt. r1.1 . yes only if rrc[7]=1; serial eeprom 001b 3 pme clock. set to 0, because pci 6520 does not support pme# signaling. yes only if rrc[7]=1; serial eeprom 0 4 auxiliary power source. set to 0, because pci 6520 does not support pme# signaling. yes only if rrc[7]=1; serial eeprom 0 5 device-specific initialization (dsi). returns 0, indicating pci 6520 does not require special initialization. yes only if rrc[7]=1; serial eeprom 0 8:6 reserved. yes no 000b 9 d 1 support. returns 1, indicating that pci 6520 supports the d 1 device power state. yes only if rrc[7]=1; serial eeprom 1 10 d 2 support. returns 1, indicating that pci 6520 supports the d 2 device power state. yes only if rrc[7]=1; serial eeprom 1 15:11 pme support. indicates the power states in which the function may assert pme#. value of 0 for any bit indicates that the function is not capable of asserting pme# while in that power state. values: xxxx1b = pme# can be asserted from d 0 xxx1xb = pme# can be asserted from d 1 xx1xxb = pme# can be asserted from d 2 x1xxxb = pme# can be asserted from d 3hot 1xxxxb = pme# can be asserted from d 3cold yes only if rrc[7]=1; serial eeprom 01111b
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-48 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-76. (pmcsr; pci:e0h) power management control/status bit description read write value after reset 1:0 power state. used to determine the current power state of a function and to set the function into a new power state. values: 00b = d 0 (default) 01b = d 1 ; valid only if pmc[9]=1; pci:deh 10b = d 2 ; valid only if pmc[10]=1; pci:deh 11b = d 3hot ; if bpcc_en=1, s_clko[4:0] are stopped yes yes; serial eeprom 00b 7:2 reserved. yes no 0h 8 pme enable. set to 0, because pci 6520 does not support pme# signaling. yes yes; serial eeprom 0 12:9 data select. returns 0h, indicating pci 6520 does not return dynamic data. yes only if rrc[7]=1; serial eeprom 0h 14:13 data scale. returns 00b when read. pci 6520 does not return dynamic data. yes no 00b 15 pme status. set to 0, because pci 6520 does not support pme# signaling. yes yes; serial eeprom 0 register 6-77. (pmcsr_bse; pci:e2h) pmcsr bridge supports extensions bit description read write value after reset 5:0 reserved. yes no 0h 6 b 2 /b 3 support for d 3hot . reflects bpcc_en input pin state. value of 1 indicates that when pci 6520 is programmed to d 3hot state, the secondary bus clock is stopped. yes no ? 7 bus power control enable. reflects bpcc_en input pin state. value of 1 indicates that the secondary bus power management state follows that of pci 6520, with one exception?d 3hot . yes no ? register 6-78. (pmcdata; pci:e3h) power management data bit description read write value after reset 7:0 power management data. serial eeprom or read-only register (ror) write controlled loadable, but is read-only during normal operation. yes only if rrc[7]=1; serial eeprom 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-49 6?registers 6.1.2.20 vpd capability register 6-79. (pvpdid; pci:e8h) vital product data capability id bit description read write value after reset 7:0 vital product data capability id. pci-sig-issued capability id for vpd is 03h. yes no 03h register 6-80. (pvpd_next; pci:e9h) vital product data next capability pointer bit description read write value after reset 7:0 next_cap pointer . provides offset into pci configuration space for the pci-x capability location in the new capabilities linked list. yes no f0h register 6-81. (pvpdad; pci:eah) vital product data address bit description read write value after reset 1:0 reserved. yes no 00b 7:2 vpd address. offset into the serial eeprom to location where data is written and read. pci 6520 accesses the serial eeprom at address pvpdad[7:2]+40h. the 40h offset ensures that vpd accesses do not overwrite the pci 6520 serial eeprom configuration data stored in serial eeprom locations 00h to 3fh. yes yes 0 14:8 reserved. yes no 0h 15 vpd operation . writing 0 generates a read cycle from the serial eeprom at the vpd address specified in pvpdad[7:2]. this bit remains at logic 0 until the serial eeprom cycle is complete, at which time the bit is set to 1. data for reads is available in the vpd data register (pvpdata; pci:ech). writing 1 generates a write cycle to the serial eeprom at the vpd address specified in pvpdad[7:2]. remains at logic 1, until the serial eeprom cycle is completed, at which time the bit is cleared to 0. place data for writes into the vpd data register. yes yes 0 register 6-82. (pvpdata; pci:ech) vpd data bit description read write value after reset 31:0 vpd data (serial eeprom data). the least significant byte of this register corresponds to the byte of vpd at the address specified by the vpd address register (pvpdad[7:2]; pci:eah). data is read from or written to pvpdata, using standard configuration accesses. yes yes 0h
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-50 preliminary ? 2004 plx technology, inc. all rights reserved. 6.1.2.21 pci-x capability register 6-83. (pcixcapid; pci:f0h) pci-x capability id bit description read write value after reset 7:0 pci-x capability id. pci-sig-issued capability id for pci-x is 07h. yes no 07h register 6-84. (pcix_next; pci:f1 h) pci-x next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for the location of the next capability in the new capabilities linked list. set to 0h to indicate the end of the capabilities list. yes no 0h register 6-85. (pcixssr; pc i:f2h) pci-x secondary status bit description read write value after reset 0 64-bit device. indicates the pci 6520 secondary ad interface width. values: 0 = 32-bit bus data width 1 = 64-bit bus data width yes no 1 1 133 mhz capable. indicates pci 6520 secondary interface is capable of 133 mhz operations in pci-x mode. values: 0 = maximum operating frequency is 66 mhz 1 = maximum operating frequency is 133 mhz note: hardwired to 1. yes no 1 2 split completion discarded. set if pci 6520 discards a split completion moving toward the secondary bus, because requester would not accept it. values: 0 = split completion not discarded 1 = split completion discarded yes yes/clr 0 3 unexpected split completion. set if an unexpected split completion with a requester id equal to pci 6520 secondary bus number, device number 00h, and function number 000b is received on pci 6520 secondary interface. values: 0 = no unexpected split completion received 1 = unexpected split completion received yes yes/clr 0
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-51 6?registers note: values where pcixssr[8]=1 are reserved . 4 split completion overrun. set if pci 6520 terminates a split completion on the secondary bus, with retry or disconnect at the next adb, because pci 6520 buffers are full. values: 0 = bridge accepted all split completions 1= bridge terminated a split completion, with a retry or disconnect at the next adb because the bridge buffers are full yes yes/clr 0 5 split request delayed. set if pci 6520 received a request to forward a transaction on the secondary bus, but cannot because there is insufficient s pace within the limit specified in the pci-x downstream split transaction register split transaction commitment limit bits (pcixdnstr[31:16]; pci:fch). values: 0 = bridge did not delay a split request 1 = bridge delayed a split request yes yes/clr 0 8:6 secondary clock frequency . enables configuration software to determine to which mode (and in pci-x mode, to which frequency) the pci 6520 set the secondary bus the last time s_rstout# was asserted. refer to table 6-3 for values. yes no ? 15:9 reserved. yes no 0h table 6-3. secondary clock frequency values (pcixssr[8:6]; pci:f2h) pcix100mhz s_xcap_in pcixssr[8:6] secondary bus minimum clock period x ground 000b conventional pci mode n/a x pulled low 001b 66 mhz pci-x mode 15 ns 1 pulled up 010b 100 mhz pci-x mode 10 ns 0 pulled up 011b 133 mhz pci-x mode 7.5 ns register 6-85. (pcixssr; pci:f2h) pci-x secondary status (continued) bit description read write value after reset
section 6 registers pci configuration register address mapping pci 6520cb data book, version 2.0 6-52 preliminary ? 2004 plx technology, inc. all rights reserved. register 6-86. (pcixbsr; pci:f4h) pci-x bridge status bit description read write value after reset 2:0 function number. indicates the number of this function? the number in ad[10:8] of a type 0 configuration transaction address to which this bridge responds. the function uses this number as part of its requester and completer ids (set to 000b). pci 6520 uses the bus, device, and function numbers fields to create the completer id when responding with a split completion to a read of an internal bridge register. yes no 000b 7:3 device number. indicates device number (the number in ad[15:11] of the address of a type 0 configuration transaction) assigned to pci 6520. yes no 11111b 15:8 bus number. additional addresses from which the primary bus number register contents (in the type 01h configuration space header) are read. yes no ? 16 64-bit device. indicates the bridge ad bus data width. this bit is the inverse of the dev64# input. values: 0 = 32-bit bus data width 1 = 64-bit bus data width yes no inverse of dev64# input 17 133 mhz capability. indicates bridge primary interface is capable of 133 mhz operations in pci-x mode. values: 0 = device maximum frequency is 66 mhz 1 = device maximum frequency is 133 mhz yes no 1 18 split completion discard. set if pci 6520 discards a split completion, because the requester on the primary bus would not accept it. values: 0 = split completion not discarded 1 = split completion discarded yes yes/clr 0 19 unexpected split completion. set if an unexpected split completion with a requester id equal to pci 6520 primary bus, device, and function numbers is received on the bridge primary bus. values: 0 = no unexpected split completion was received 1 = unexpected split completion was received yes yes/clr 0 20 split request delay. set if pci 6520 terminates a split completion on the primary bus, with retry or disconnect at the next adb, because the bridge buffers are full. used by algorithms that optimize the upstream split transaction commitment limit register setting. values: 0 = bridge accepted all split completions 1 = bridge terminated a split completion with retry or disconnect yes yes/clr 0 21 split completion overrun. set when pci 6520 receives a request to forward a transaction on the primary bus, but cannot because there is insuffic ient space within the limit specified in the pci-x upstream split transaction register split transaction commitment limit bits (pcixupstr[31:16]; pci:f8h). values: 0 = bridge did not delay a split request 1= bridge delayed a split request yes yes/clr 0 31:22 reserved. yes no 0h
section 6 pci configuration register address mapping registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 6-53 6?registers note: pcixupstr controls the bridge buffer behavior for forwarding split transactions from a secondary requester to a primary bus completer. note: pcixdnstr controls the bridge buffer behavior for forwarding split transactions from a primary bus requester to a secondary bus completer. register 6-87. (pcixupstr; pci:f8 h) pci-x upstream split transaction bit description read write value after reset 15:0 split transaction capacity. pci 6520 stores split completions for memory reads in the same buffer as split completions for i/o and configuration reads and writes. indicates the buffer size, in adq numbers, for storing split completions for memory reads for requesters on the secondary bus addressing completers on the primary bus. yes no 32d 31:16 split transaction commitment limit or outstanding adq limit. indicates the cumulative sequence size for pci-x memory read transactions forwarded by pci 6520 from requesters on the secondary bus addressing completers on the primary bus. also indicates upstream split transaction size of those types the pci 6520 is allowed to commit to at one time. yes yes 32d register 6-88. (pcixdnstr; pci:fch) pci-x downstream split transaction bit description read write value after reset 15:0 split transaction capacity. pci 6520 stores split completions for memory reads in the same buffer as split completions for i/o and configuration reads and writes. indicates the buffer size, in adq numbers, for storing split completions for memory reads for requesters on the primary bus addressing comple ters on the secondary bus. yes no 32d 31:16 split transaction commitment limit or outstanding adq limit. indicates the cumulative sequence size for pci-x memory read transactions forwarded by pci 6520 from requesters on the secondary bus addressing completers on the primary bus. also indicates downstream split transaction size of those types the pci 6520 is allowed to commit to at one time. yes yes 32d

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 7-1 7?serial eeprom 7 serial eeprom this section describes information specific to the pci 6520 serial eeprom interface and use?access, autoload mode, and data structure. 7.1 overview important note: erroneous serial eeprom data can cause the pci 6520 to lock the system. provide an optional switch or jumper to disable the serial eeprom in board designs. the pci 6520 provides a two-wire interface to a serial eeprom device. the interface can control an issi is24c02 or compatible part, which is organized as 256 x 8 bits. the serial eeprom is used to initialize the internal pci 6520 registers, and alleviates the need for user software to configure the pci 6520. if a programmed serial eeprom is connected, the pci 6520 automatically loads data from the serial eeprom after p_rstin# de-assertion. the serial eeprom data structure is defined in section 7.4.1. the serial eeprom interface is organized on a 16-bit base in little endian format, and the pci 6520 supplies a 7-bit serial eeprom word address. the following pins are used for the serial eeprom interface: eepclk ?serial eeprom clock output eepdata ?serial eeprom bi-directional serial data note: the pci 6520 does not control the serial eeprom a0 to a2 address inputs. it can only access serial eeprom addresses set to 0. 7.2 serial eeprom access the pci 6520 can access the serial eeprom on a word basis, using the hardware sequencer. users access one word data by way of the pci 6520 serial eeprom control register: serial eeprom start/read/write control (eepcntrl; pci:54h) serial eeprom address (eepaddr; pci:55h) serial eeprom data (eepdata; pci:56h) before each access, software should check the auto mode cycle in progress status (eepcntrl[0]; pci:54h, same bit as start) before issuing the next start. the following is the general procedure for read/ write serial eeprom accesses: 1. program the serial eeprom address register (eepaddr; pci:55h) with the word address. 2. writes ?program word data to the serial eeprom data register (eepdata; pci:56h). reads ?proceed to the next step. 3. writes ?set the serial eeprom command and start bits (eepcntrl[1:0]=11b; pci:54h, respectively) to start the serial eeprom sequencer. reads ?set the start bit (eepcntrl[1:0]=01b; pci:54h) to start the serial eeprom sequencer. 4. when the serial eeprom read/write is complete, as indicated by the bit value of 0 (serial eeprom control register, eepcntrl[0]=0; pci:54h): writes ?data was successfully written to the serial eeprom. reads ?data was loaded into the serial eeprom data register (eepdata; pci:56h) by the serial eeprom sequencer. 7.3 serial eeprom autoload mode at reset upon pwrgd or p_rstin# going high (whichever occurs later), the pci 6520 autoloads the serial eeprom data into the internal pci 6520 registers. the pci 6520 initially reads the first offset in the serial eeprom, which should contain a valid signature value of 1516h. if the signature is correct, register autoload commences immediately commences after reset. during autoload, the pci 6520 reads sequential words from the serial eeprom and writes to the appropriate registers. if a blank serial eeprom is connected, the pci 6520 stops loading the serial eeprom contents after reading the first word, as the serial eeprom?s signature is not valid. likewise, if no serial eeprom is connected, the pci 6520 also stops loading the serial eeprom contents after attempting to read the first word.
section 7 serial eeprom serial eeprom data structure pci 6520cb data book, version 2.0 7-2 preliminary ? 2004 plx technology, inc. all rights reserved. 7.4 serial eeprom data structure following reset and the previously described conditions, the pci 6520 autoloads the registers with serial eeprom data. figure 7-1 illustrates the serial eeprom data structure. the pci 6520 accesses the serial eeprom, one word at a time. it is important to note that in the data phase, bit orders are the reverse of that in the address phase. the pci 6520 supports only serial eeprom device address 0. figure 7-1. serial eeprom data structure a c k m s b m s b l s b l s b s t o p data (n) data (n +1) a c k a c k wor d address (n) m s b l s b 0 s t a r t 10 a c k w r i t e device address 10 0 00 10 a c k a c k wor d address (n) m s b l s b w r i t e device address 0 10 0 00 s t a r t 10 a c k r e a d device address 10 0 00 a c k m s b m s b l s b l s b data (n) data (n +1) n o a c k s t o p s t a r t read wr i t e
section 7 serial eeprom data structure serial eeprom pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 7-3 7?serial eeprom 7.4.1 serial eeprom address and correspondi ng pci 6520 registers table 7-1. serial eeprom address and corresponding pci 6520 registers serial eeprom byte address pci configuration offset description 00h ? 01h ? serial eeprom signature. autoload proceeds only if it reads a value of 1516h on the first word loaded. value: 1516h = valid signature; otherwise, disables autoloading. 02h ? region enable. enables or disables certain regions of the pci configuration space from being loaded from the serial eeprom. valid combinations are: bit 0 = reserved. bits [4:1] = 0000b = stops autoload at serial eeprom offset 03h = group 1. 0001b = stops autoload at serial eeprom offset 13h = group 2. 0011b = stops autoload at serial eeprom offset 23h = group 3. 0111b, 1111b = reserved. other combinations are undefined. bits [7:5] = reserved. 03h ? enable miscellaneous functions. bits [7:0] = reserved. end of group 1 04h ? 05h 00h ? 01h vendor id (pciidr[15:0]). 06h ? 07h 02h ? 03h device id (pciidr[31:16]). 08h ? reserved. 09h 09h class code. contains low byte of class code register (pciccr[7:0]). 0ah ? 0bh 0ah ? 0bh class code higher bytes. contains upper bytes of class code register (pciccr[23:8]). 0ch 0eh header type (pcihtr). 0dh 09h reserved. 0eh ? 0fh 0ah ? 0bh reserved. 10h 0eh reserved. 11h 0fh built-in self test (bist) (pcibistr). not supported . set to 0. 12h ? 13h 50h internal arbiter control (iacntrl). end of group 2 14h 44h primary flow-through control (pftcr). 15h 45h timeout control (tocntrl). 16h ? 17h 46h ? 47h miscellaneous options (mscopt). 18h 48h primary initial prefetch count (pitlpcnt). 19h 49h secondary initial prefetch count (sitlpcnt). 1ah 4ah primary incremental prefetch count (pincpcnt). 1bh 4bh secondary incremental prefetch count (sincpcnt). 1ch 4ch primary maximum prefetch count (pmaxcnt). 1dh 4dh secondary maximum prefetch count (smaxcnt). 1eh 4eh secondary flow-through control (sftcr). 1fh e3h power management data (pmcdata). 20h ? 21h e0h power management control/status (pmcsr). 22h ? 23h deh power management capabilities (pmc).
section 7 serial eeprom serial eeprom data structure pci 6520cb data book, version 2.0 7-4 preliminary ? 2004 plx technology, inc. all rights reserved. end of group 3 24h ? 25h 2ch reserved. must be 0. 26h ? 27h 2eh reserved. must be 0. end of group 4 28h ? 3fh ? reserved. must be 0. end of group 5 table 7-1. serial eeprom address and corresponding pci 6520 registers (continued) serial eeprom byte address pci configuration offset description
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-1 8?pci bus operation 8 pci bus operation this section describes pci transactions to which the pci 6520 responds and those it initiates when operating with one or both of its interfaces in conventional pci mode. 8.1 conventional pci transactions table 8-1 lists the conventional pci command codes and transaction types to which the pci 6520 responds and initiates. the master and target columns indicate support for transactions wherein the pci 6520 initiates transactions as a master, and responds to transactions as a target, on the primary and secondary buses. table 8-1. conventional pci transactions cbe[3:0]# transaction type initiates as master responds as target primary secondary primary secondary 0000b interrupt acknowledge (not supported) nnnn 0001b special cycle (not supported) yynn 0010b i/o read y y y y 0011b i/o write y y y y 0100b reserved nnnn 0101b reserved nnnn 0110b memory read y y y y 0111b memory write y y y y 1000b reserved nnnn 1001b reserved nnnn 1010b configuration read n y y n 1011b configuration write type 1 y y type 1 1100b memory read multiple y y y y 1101b dual address cycle (dac) y y y y 1110b memory read line y y y y 1111b memory write and invalidate y y y y
section 8 pci bus operation single address phase pci 6520cb data book, version 2.0 8-2 preliminary ? 2004 plx technology, inc. all rights reserved. as indicated in table 8-1, the pci 6520 does not support the following conventional pci commands?it ignores them and reacts to these commands as follows: reserved ?the pci 6520 does not generate reserved command codes. interrupt acknowledge ?the pci 6520 never initiates an interrupt acknowledge transaction and, as a target, it ignores interrupt acknowledge transactions. interrupt acknowledge transactions are expected to reside entirely on the primary pci bus closest to the host bridge. special cycle ?the pci 6520 does not respond to special cycle transactions. to generate special cycle transactions on other pci buses (downstream or upstream), use a type 1 configuration command. type 0 configuration write ?the pci 6520 does not generate type 0 configuration write transactions on the primary interface. 8.2 single address phase the pci 6520 32-bit address uses a single address phase. this address is driven on ad[31:0], and the bus command is driven on p_cbe[3:0]#. the pci 6520 supports only the linear increment address mode, which is indicated when the lower two address bits equal 00b. if either of the lower two address bits is equal to a non-zero value, the pci 6520 automatically disconnects the transaction after the first data transfer. 8.3 dual address phase the pci 6520 supports the dual address cycle (dac) bus command to transfer 64-bit addresses. in dac transactions, the first address phase occurs during the initial frame# assertion, and the second address phase occurs one clock later. during the first address phase, the dac command is presented on cbe[3:0]#, and the lower 32 bits of the address on ad[31:0]. the second address phase retains the cycle command on cbe[3:0]#, and the upper 32 bits of the address on ad[31:0]. when a 64-bit master uses dac, the master must provide the upper 32 bits of the address on ad[63:32] and the command on cbe[7:4]# during the address phases of both transactions to allow 64-bit targets additional time to decode the transaction. dacs are used to access locations that are not in the first 4 gb of pci memory space. addresses in the first 4 gb of pci memory space always use a single address cycle (sac). the pci 6520 supports dacs in the downstream and upstream directions. the pci 6520 responds to dacs for the following commands only: memory write memory write and invalidate memory read memory read line memory read multiple the pci 6520 forwards dacs downstream when their addresses fall within prefetchable memory space. dacs originating on the secondary bus, with addresses outside prefetchable memory space, are forwarded upstream. 8.4 device select (devsel#) generation the pci 6520 performs positive address decoding when accepting transactions on the primary or secondary bus. the pci 6520 never subtractively decodes. medium devsel# timing is used for 33 mhz operation. slow devsel# timing is used for 66 mhz operation. 8.5 data phase depending on the command type, the pci 6520 can support multiple data phase conventional pci transactions. write transactions are treated as posted write or delayed write transactions. table 8-2 lists the forwarding method used for each type of write operation. table 8-2. write transaction forwarding transaction type forwarding method memory write posted memory write and invalidate i/o write delayed type 1 configuration write
section 8 data phase pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-3 8?pci bus operation 8.5.1 posted write transactions when the pci 6520 determines that a memory write transaction is to be forwarded across the bridge, the pci 6520 asserts devsel# with slow timing and trdy# in the same cycle, provided that sufficient buffer space is available in the posted write data queue, and that the queue contains fewer than four outstanding posted transactions. the pci 6520 can accept one dual-dword of write data every pci clock cycle ( that is , no target wait states are inserted). up to 256 bytes of posted write data are stored in internal posted write buffers and eventually delivered to the target. the pci 6520 continues to accept write data until one of the following occurs: initiator normally terminates the transaction cache line boundary or an aligned 4-kb boundary is reached, depending on transaction type posted write data buffer fills when one of the last two events occurs, the pci 6520 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. after the posted write transaction is selected for completion, the pci 6520 requests ownership of the target bus. this can occur while the pci 6520 is receiving data on the initiator bus. after the pci 6520 has ownership of the target bus, and the target bus is detected in the idle condition, the pci 6520 initiates the write cycle and continues to transfer write data until all write data corresponding to that transaction is delivered, or a target termination is received. if write data exists in the queue, the pci 6520 can drive one dual-dword of write data each pci clock cycle. if write data is flowing through the pci 6520 and the initiator stalls, the pci 6520 inserts wait states on the target bus if the queue empties. the pci 6520 ends the transaction on the target bus when one of the following conditions is met: all posted write data was delivered to the target target returns a target disconnect or retry (the pci 6520 starts another transaction to deliver the remaining write data) target returns a target abort (the pci 6520 discards remaining write data) the master latency timer expires, and the pci 6520 no longer retains the target bus grant (the pci 6520 starts another transaction to deliver the remaining write data). 8.5.2 memory write and invalidate transactions memory write and invalidate transactions guarantee the transfer of entire cache lines. by default, the pci 6520 retries a memory write and invalidate cycle until there is space for one or more cache lines of data in the internal buffers. the pci 6520 then completes the transaction on the secondary bus as a memory write and invalidate cycle. the pci 6520 can also be programmed to accept memory write and invalidate cycles under the same conditions as normal memory writes. in this case, if the write buffer fills before an entire cache line is transferred, the pci 6520 disconnects and completes the write cycle on the secondary bus as a normal memory write cycle by way of the miscellaneous options register memory write and invalidate control bit (mscopt[12]; pci:46h). the pci 6520 disconnects memory write and invalidate commands at aligned cache line boundaries. the cache line size register (pciclsr; pci:0ch) cache line size value provides the number of dwords in a cache line. for the pci 6520 to generate memory write and invalidate transactions, this cache line size value must be written to a value of 08h, 10h, or 20h dwords. if an invalid cache line size is programmed, wherein the value is 0, not a power of two, or greater than 20h dwords, the pci 6520 sets the cache line size to the minimum value of 08h. the pci 6520 always disconnects on the cache line boundary. when the memory write and invalidate transaction is disconnected before a cache line boundary is reached (typically because the posted write data buffer fills), the transaction is converted to a memory write transaction. 8.5.3 delayed write transactions a delayed write transaction forwards i/o write and type 1 configuration cycles by way of the pci 6520, and is limited to a single dword data transfer. when a write transaction is first detected on the initiator bus, the pci 6520 claims the access and
section 8 pci bus operation data phase pci 6520cb data book, version 2.0 8-4 preliminary ? 2004 plx technology, inc. all rights reserved. returns a target retry to the initiator. during the cycle, the pci 6520 samples the bus command, address, and address parity bits. the pci 6520 also samples the first data dword, byte enable bits, and data parity. cycle information is placed into the delayed transaction queue if there are no other existing delayed transactions with the same cycle information, and if the delayed transaction queue is not full. when the pci 6520 schedules a delayed write transaction to be the next cycle to complete based on its ordering constraints, the pci 6520 initiates the transaction on the target bus. the pci 6520 transfers the write data to the target. if the pci 6520 receives a target retry in response to the write transaction on the target bus, the pci 6520 continues to repeat the write transaction until the data transfer is complete, or an error condition is encountered. if the pci 6520 is unable to deliver write data after 2 24 attempts (programmable through the timeout control register maximum retry counter control bits, tocntrl[2:0]; pci:45h), the pci 6520 ceases further write attempts and returns a target abort to the initiator. the delayed transaction is removed from the delayed transaction queue. the pci 6520 also asserts p_serr# if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), after the pci 6520 has completed data delivery and retains all complete cycle information in the queue, the pci 6520 claims the access and returns trdy# to the initiator, indicating that the write data was transferred. if the initiator requests multiple dwords, the pci 6520 asserts stop#, in conjunction with trdy#, to signal a target disconnect. only those bytes of write data with valid byte enable bits are compared. if any byte enable bits are disabled (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write transaction before the data is transferred to the target, the pci 6520 returns a target retry to the initiator. the pci 6520 continues to return a target retry to the initiator until write data is delivered to the target or an error condition is encountered. when the write transaction is repeated, the pci 6520 does not make a new entry into the delayed transaction queue. the pci 6520 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of four values, selectable through the primary and secondary bridge control register master timeout bits (bcntrl[8:9]; pci:3eh), as well as the timeout control register master timeout divider bits (tocntrl[7:4]; pci:45h). if the discard timer expires before the write cycle is retried, the pci 6520 discards the delayed write transaction from the delayed transaction queue. the pci 6520 also conditionally asserts p_serr#.
section 8 data phase pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-5 8?pci bus operation 8.5.4 write transaction address boundaries the pci 6520 imposes internal address boundaries when accepting write data. the aligned address boundaries are used to prevent the pci 6520 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. when the aligned address boundaries are reached (per conditions listed in table 8-3), the pci 6520 returns a target disconnect to the initiator. 8.5.5 buffering multiple write transactions the pci 6520 continues to accept posted memory write transactions if space for at least 1 dword of data in the posted write data buffer remains and there are fewer than four outstanding posted memory write cycles. if the posted write data buffer fills before the initiator terminates the write transaction, the pci 6520 returns a target disconnect to the initiator. delayed write transactions are posted when one or more open entries exist in the delayed transaction queue. the pci 6520 can queue up to four posted write transactions and four delayed transactions in both the downstream and upstream directions. 8.5.6 read transactions delayed read forwarding is used for all read transactions that cross the pci 6520. delayed read transactions are treated as prefetchable or non-prefetchable. table 8-4 delineates the read behavior (prefetchable or non-prefetchable) for each type of read operation. table 8-3. write transaction disconnect address boundaries transaction type condition aligned address boundary delayed write all disconnects after one data transfer posted memory write memory write disconnect control bit = 0 1 4-kb aligned address boundary memory write disconnect control bit = 1 1 1. memory write disconnect control bit is located in the chip control register in configuration space (ccntrl[1]; pci:40h). disconnects at cache line boundary posted memory write and invalidate cache line size = 8h 8h-dword aligned address boundary cache line size = 10h 10h-dword aligned address boundary cache line size = 12h 12h-dword aligned address boundary table 8-4. read transaction prefetching transaction type read behavior i/o read never prefetches configuration read memory read downstream?prefetches if addres s is in prefetchable space upstream?prefetches if prefetch disable is off (default) memory read line always prefetches if request is for more than one data transfer memory read multiple
section 8 pci bus operation data phase pci 6520cb data book, version 2.0 8-6 preliminary ? 2004 plx technology, inc. all rights reserved. 8.5.7 prefetchable read transactions a prefetchable read transaction is a read transaction wherein the pci 6520 performs speculative dword reads, transferring data from the target before the initiator requests the data. this behavior allows a prefetchable read transaction to consist of multiple data transfers. only the first byte enable bits can be forwarded. the pci 6520 enables all byte enable bits of subsequent transfers. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as memory read transactions that fall into prefetchable memory space. the amount of prefetched data depends on the transaction type. the amount of prefetching may also be affected by the amount of free space in the pci 6520 read fifo and by the read address boundaries encountered. in addition, there are several pci 6520-specific registers that can be used to optimize read prefetch behavior. prefetching should not be used for those read transactions that cause side effects on the target device ( that is , control and status registers, fifos, and so forth). the target device bars indicate whether a memory address region is prefetchable. 8.5.8 non-prefetchable read transactions a non-prefetchable read transaction is a read transaction issued by the initiator into a non-prefetchable region. the transaction is used for i/o and configuration read transactions, as well as for memory reads from non-prefetchable memory space. in this case, the pci 6520 requests only 1 dword from the target and disconnects the initiator after delivery of the first dword of read data. use non-prefetchable read transactions for regions in which extra read transactions could have side effects ( such as in fifo memory or the control registers). if it is important to retain the byte enable bit values during the data phase of cycles forwarded across the bridge, use non-prefetchable read transactions. if these locations are mapped into memory space, use the memory read command and map the target into non-prefetchable (memory- mapped i/o) memory space to utilize non-prefetching behavior. 8.5.9 read prefetch address boundaries the pci 6520 imposes internal read address boundaries on read prefetching. the pci 6520 uses the address boundary to calculate the initial amount of prefetched data. during read transactions to prefetchable regions, the pci 6520 prefetches data until it reaches one of these aligned address boundaries, unless the target signals a target disconnect before reaching the read prefetch boundary. after reaching the aligned address boundary, the pci 6520 may optionally continue prefetching data, depending on certain conditions. (refer to section 18, ?pci flow-through optimization.?) when finished transferring read data to the initiator, the pci 6520 returns a target disconnect with the last data transfer, unless the initiator completes the transaction before delivering all the prefetched read data. remaining prefetched data is discarded. prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4-kb address boundary, or until the initiator de-asserts frame#. table 8-5 delineates the read prefetch address boundaries for read transactions during non-flow- through mode. table 8-5. read prefetch address boundaries transaction type address space prefetch aligned address boundary configuration read ? 1 dword (no prefetch) i/o read memory read non-prefetchable memory read prefetchable configured by way of prefetch count registers memory read line memory read multiple
section 8 data phase pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-7 8?pci bus operation 8.5.10 delayed read requests the pci 6520 treats all read transactions as delayed read transactions ( that is , the read request from the initiator is posted into a delayed transaction queue). read data from the target is placed into the read data queue directed toward the initiator bus interface and transferred to the initiator when the initiator repeats the read transaction. when the pci 6520 accepts a delayed read request, it first samples the read address, read bus command, and address parity. when irdy# is asserted, the pci 6520 samples the byte enable bits for the first data phase. this information is entered into the delayed transaction queue. the pci 6520 terminates the transaction by signaling a target retry to the initiator. upon receiving the target retry, the initiator must to continue to repeat the same read transaction until at least one data transfer completes, or until it receives a target response other than a target retry (master or target abort). 8.5.11 delayed read completion with target when a delayed read request is scheduled to be executed, the pci 6520 arbitrates for the target bus and initiates the read transaction, using the exact read address and read command captured from the initiator during the initial delayed read request. if the read transaction is non-prefetchable, the pci 6520 drives the captured byte enable bits during the next cycle. if the transaction is a prefetchable read transaction, the pci 6520 drives the captured (first) byte enable bits, followed by 0 for the subsequent data phases. if the pci 6520 receives a target retry in response to the read transaction on the target bus, it repeats the read transaction until at least one data transfer completes or it encounters an error condition. if the transaction is terminated by way of a normal master termination or target disconnect after at least one data transfer is complete, the pci 6520 does not initiate further attempts to read additional data. if the pci 6520 is unable to obtain read data from the target after 2 24 attempts (default), the pci 6520 ceases further read attempts and returns a target abort to the initiator. the delayed transaction is removed from the delayed transaction queue. the pci 6520 also asserts p_serr# if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). after receiving devsel# and trdy# from the target, the pci 6520 transfers the data stored in the internal read fifo, then terminates the transaction. the pci 6520 can accept 1 dword/qword of read data during each pci clock cycle?no master wait states are inserted. the number of dwords/qwords transferred during a delayed read transaction depends on the conditions delineated in table 8-5 (assuming no target disconnect is received). 8.5.12 delayed read completion on initiator bus when the delayed read transaction completes on the target bus, the delayed read data is at the head of the read data queue. when all ordering constraints with posted write transactions are satisfied, the pci 6520 transfers the data to the initiator when the initiator repeats the transaction. for memory read transactions, the pci 6520 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. the pci 6520 returns a target disconnect along with the transfer of the last dword of read data to the initiator. if the pci 6520 initiator terminates the transaction before all read data is transferred, the remaining read data in the data buffers is discarded. when the master repeats the transaction and starts transferring prefetchable read data from the data buffers while the read transaction on the target bus is in progress, and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because data is flowing from the target to the initiator through the data buffers, long read bursts can be sustained. in this case, the read transaction is allowed to continue until the initiator terminates the transaction, an aligned 4-kb address boundary is reached, or the buffer fills, whichever occurs first. when the buffer empties, the pci 6520 reflects the stalled condition to the initiator by de-asserting trdy# for a maximum of eight clock periods until more read data is available; otherwise, the pci 6520 disconnects the cycle. when the initiator terminates the transaction, the pci 6520 de-assertion
section 8 pci bus operation data phase pci 6520cb data book, version 2.0 8-8 preliminary ? 2004 plx technology, inc. all rights reserved. of frame# on the initiator bus is forwarded to the target bus. any remaining read data is discarded. the pci 6520 implements a discard timer (bcntrl[9 or 8]; pci:3eh) that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. if the initiator does not repeat the read transaction before the discard timer expires, the pci 6520 discards the read transaction, discards the read data from its queues, and conditionally asserts p_serr#. the pci 6520 has the capability to post multiple delayed read requests, up to a maximum of four in both directions. if an initiator starts a read transaction that matches the address and read command of a queued read transaction, the current read command is not stored because it is contained in the delayed transaction queue. 8.5.13 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configuration commands. all registers are accessible only in configuration space. in addition to accepting configuration transactions for initialization of its own configuration space, the pci 6520 forwards configuration transactions for device initialization in hierarchical pci bus systems, as well as special cycle generation. to support hierarchical pci bus systems, type 0 and type 1 configuration transactions are specified. type 0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. type 0 configuration transactions are identified by the configuration command and the lowest two bits of the address are set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or a special cycle is to be generated on another pci bus. type 1 configuration commands are identified by the configuration command and the lowest two address bits are set to 01b. the register number is found in both type 0 and type 1 formats and provides the dword address of the configuration register to be accessed. the function number is also included in both type 0 and type 1 formats, and indicates which function of a multi-function device is to be accessed. for single-function devices, this value is not decoded. type 1 configuration transaction addresses also include five bits, designating the device number that identifies the target pci bus device to be accessed. in addition, the bus number in type 1 transactions specifies the target pci bus. 8.5.14 pci 6520 type 0 access configuration space is accessed by a type 0 configuration transaction on the primary interface. configuration space is not accessible from the secondary bus. the pci 6520 responds to a type 0 configuration transaction by asserting p_devsel# when the following conditions are met during the address phase: bus command is a configuration read or write transaction. lower two address bits on p_ad[1:0] must be 01b. p_idsel must be asserted. pci 6520 limits all configuration accesses to a single dword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. because read transactions to configuration space do not have side effects, all bytes in the requested dword are returned, regardless of the byte enable bit values. type 0 configuration read and write transactions do not use data buffers ( that is , these transactions are immediately completed, regardless of the data buffers state). the pci 6520 ignores all type 0 transactions initiated on the secondary interface. 8.5.15 type 1-to-type 0 translation type 1 configuration transactions are specifically used for device configuration in a hierarchical pci bus system. a pci-to-pci bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration commands are used when the configuration access is intended for a pci device that resides on a pci bus other than the one where the type 1 transaction is generated. the pci 6520 performs a type 1-to-type 0 translation when the type 1 transaction is generated on the primary bus and is intended for a device attached
section 8 data phase pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-9 8?pci bus operation directly to the secondary bus. the pci 6520 must convert the configuration command to a type 0 format, enabling the secondary bus device to respond to the command. type 1-to-type 0 translations are performed only in the downstream direction ( that is , the pci 6520 generates a type 0 transaction only on the secondary bus, and never on the primary bus). the pci 6520 responds to a type 1 configuration transaction and translates the transaction into a type 0 transaction on the secondary bus when the following conditions are met during the address phase: lower two address bits on p_ad[1:0] are 01b bus number in address field p_ad[23:16] is equal to the secondary bus number register value in configuration space (pcisbno; pci:19h) bus command on p_cbe[3:0]# is a configuration read or write transaction when translating a type 1 transaction to a type 0 transaction on the secondary interface, the pci 6520 performs the following translations to the address: sets the lower two address bits on s_ad[1:0] to 00b decodes the device number and drives the bit pattern specified in table 8-6 on s_ad[31:16] for the purpose of asserting the device?s idsel signal sets s_ad[15:11] to 0h leaves the function and register number fields unchanged the pci 6520 asserts unique address lines, based on the device number. these address lines may be used as secondary idsel signals. address line mapping depends on the device number in the type 1 address bits, p_ad[15:11]. the pci 6520 uses the mapping presented in table 8-6. the pci 6520 can assert up to 16 unique address lines to be used as secondary idsel signals for up to 16 secondary bus devices, for device numbers ranging from 0 to 15. because of the pci bus electrical loading constraints, more than 16 idsel signals should not be necessary. however, if more than 15 device numbers are needed, an external method of generating idsel lines must be used, and the upper address bits are not asserted. the configuration transaction is translated and passed from primary-to-secondary bus. if an idsel pin is not asserted to a secondary device, the transaction terminates in a master abort. the pci 6520 forwards type 1-to-type 0 configuration read or write transactions as delayed transactions. type 1-to-type 0 configuration read or write transactions are limited to a single 32-bit data transfer. when type 1-to-type 0 configuration cycles are forwarded, address stepping is used, and a valid address is driven on the bus before frame# assertion. type 0 configuration address stepping is programmable through the miscellaneous options register address step control bits (mscopt[6:4]; pci:46h).
section 8 pci bus operation data phase pci 6520cb data book, version 2.0 8-10 preliminary ? 2004 plx technology, inc. all rights reserved. table 8-6. device number to idsel s_ad pin mapping device number p_ad[15:11] secondary idsel s_ad[31:16] s_ad bit 0h 00000b 0000_0000_0000_0001b 16 1h 00001b 0000_0000_0000_0010b 17 2h 00010b 0000_0000_0000_0100b 18 3h 00011b 0000_0000_0000_1000b 19 4h 00100b 0000_0000_0001_0000b 20 5h 00101b 0000_0000_0010_0000b 21 6h 00110b 0000_0000_0100_0000b 22 7h 00111b 0000_0000_1000_0000b 23 8h 01000b 0000_0001_0000_0000b 24 9h 01001b 0000_0010_0000_0000b 25 10h 01010b 0000_0100_0000_0000b 26 11h 01011b 0000_1000_0000_0000b 27 12h 01100b 0001_0000_0000_0000b 28 13h 01101b 0010_0000_0000_0000b 29 14h 01110b 0100_0000_0000_0000b 30 15h 01111b 1000_0000_0000_0000b 31 special cycle 1xxxxb 0000_0000_0000_0000b ?
section 8 data phase pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-11 8?pci bus operation 8.5.16 type 1-to-type 1 forwarding type 1-to-type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of pci-to-pci bridges are used. when the pci 6520 detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, the pci 6520 forwards the transaction unchanged to the secondary bus. ultimately, this transaction is translated to a type 0 configuration command or to a special cycle transaction by a downstream pci-to-pci bridge. downstream type 1-to-type 1 forwarding occurs when the following conditions are met during the address phase: lower two address bits on ad[1:0] are equal to 01b bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register (pcisbno; pci:19h) and upper limit (inclusive) in the subordinate bus number register (pcisubno; pci:1ah) bus command is a configuration read or write transaction the pci 6520 also supports type 1-to-type 1 upstream configuration write transaction forwarding to support upstream special cycle generation. a type 1 configuration command is forwarded upstream when the following conditions are met: lower two address bits on ad[1:0] are equal to 01b bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register (pcisbno; pci:19h) and upper limit (inclusive) in the subordinate bus number register (pcisubno; pci:1ah) device number in address bits ad[15:11] is equal to 11111b function number in address bits ad[10:8] is equal to 111b bus command is a configuration write transaction pci 6520 forwards type 1-to-type 1 configuration write transactions as delayed transactions, limited to a single data transfer 8.5.17 special cycles the type 1 configuration mechanism is used to generate special cycle transactions in hierarchical pci systems. special cycle transactions are ignored by operating as a target and are not forwarded across the bridge. special cycle transactions can be generated from type 1 configuration write transactions in either the downstream or upstream direction. the pci 6520 initiates a special cycle on the target bus when a type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: lower two address bits on ad[1:0] are equal to 01b device number in address bits ad[15:11] is equal to 11111b function number in address bits ad[10:8] is equal to 111b register number in address bits ad[7:2] is equal to 0h bus number is equal to the secondary bus number register value in configuration space (pcisbno; pci:19h) for downstream forwarding, or equal to the primary bus number register value in configuration space (pcipbno; pci:18h) for upstream forwarding bus command on the initiator cbe bus is a configuration write command when the pci 6520 initiates a transaction on the target interface, the bus command is changed from configuration write to special cycle. the address and data are forwarded, unchanged. devices that use special cycle ignore the address and decode only the bus command. the data phase contains the special cycle message. the transaction is forwarded as a delayed transaction because special cycles complete as master aborts. after the transaction is completed on the target bus, through master abort condition detection, the pci 6520 responds with trdy# to the next attempt of the configuration transaction from the initiator. if more than one data transfer is requested, the pci 6520 responds with a target disconnect operation during the first data phase.
section 8 pci bus operation conventional pci mode transaction termination pci 6520cb data book, version 2.0 8-12 preliminary ? 2004 plx technology, inc. all rights reserved. 8.6 conventional pci mode transaction termination this subsection describes how the pci 6520 returns transaction termination conditions to the initiator. the initiator can terminate transactions with one of the following types of termination: normal termination ?occurs when the initiator de-asserts frame# at the beginning of the last data phase, and de-asserts irdy# at the end of the last data phase in conjunction with trdy# or stop# assertion from the target. master abort ?occurs when no target response is detected. when the initiator does not detect the devsel# signal from the target within five clock cycles after asserting frame#, the initiator terminates the transaction with a master abort. if frame# is asserted, the initiator de-asserts frame# on the next cycle, then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# is de-asserted. if frame# was de-asserted, irdy# can be de-asserted on the next clock cycle following master abort condition detection. the target can terminate transactions with one of the following types of termination: normal termination ?trdy# and devsel# are asserted in conjunction with frame# de-assertion and irdy# assertion. target retry ?stop# and devsel# are asserted without trdy# during the first data phase. no data transfers during the transaction. this transaction must be repeated. target disconnect (with data transfer) ? devsel# and stop# are asserted with trdy#. indicates that this is the last data transfer of the transaction. target disconnect (without data transfer) ? stop# and devsel# are asserted without trdy# after previous data transfers. indicates that no further data transfers are made during this transaction. target abort ?stop# is asserted without devsel# and trdy#. indicates that the target is never able to complete this transaction. devsel# must be asserted for at least one cycle during the transaction before the target abort is signaled. 8.6.1 pci 6520-initiated master termination as an initiator, the pci 6520 uses normal termination if devsel# is returned by the target within five clock cycles of pci 6520 frame# assertion on the target bus. in this case, the pci 6520 terminates a transaction when the following conditions are met: during delayed write transactions, a single dword/ qword is delivered. during non-prefetchable read transactions, a single dword/qword is transferred from the target. during prefetchable read transactions, a prefetch boundary is reached. for posted write transactions, all write data for the transaction is transferred from data buffers to the target. for burst transfers ( except memory write and invalidate transactions), the master latency timer expires and the pci 6520 bus grant is de-asserted. target terminates the transaction with a retry, disconnect, or target abort. if the pci 6520 is delivering posted write data when it terminates the transaction because the master latency timer expired, the pci 6520 initiates another transaction to deliver the remaining write data. the transaction address is updated to reflect the address of the current dword to be delivered. if the pci 6520 is delivering posted write data when it terminates the transaction because the master latency timer expires, the pci 6520 initiates another transaction to deliver the remaining write data. the transaction address is updated to reflect the current dword address to be delivered. if the pci 6520 is prefetching read data when it terminates the transaction because the master latency timer expired, the pci 6520 does not repeat the transaction to obtain additional data.
section 8 conventional pci mode transaction termination pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-13 8?pci bus operation 8.6.2 master abort received by pci 6520 if the initiator initiates a transaction on the target bus and does not detect devsel# returned by the target within five clock cycles of frame# assertion, the pci 6520 terminates the transaction, as specified in the bridge control register master abort mode bit (bcntrl[5]; pci:3eh). for delayed read and write transactions, the pci 6520 can assert trdy# and return ffff_ffffh for reads, or return a target abort. serr# is also optionally asserted. when a master abort is received in response to a posted write transaction, the pci 6520 discards the posted write data and makes no further attempts to deliver the data. the pci 6520 sets the status register received master abort bit when the master abort is received on the primary bus (pcisr[13]=1; pci:06h), or the secondary status register received master abort bit when the master abort is received on the secondary interface (pcissr [13]=1; pci:1eh). when the master abort mode bit is set and a master abort is detected in response to a posted write transaction, the pci 6520 also asserts p_serr#, if enabled (pcicr[8]=1; pci:04h), but not disabled by the device-specific p_serr# disable for master aborts that occur during posted write transactions. (refer to table 8-7.) 8.6.3 target termination received by pci 6520 when the pci 6520 initiates a transaction on the target bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination: normal termination (upon frame# de-assertion) target retry target disconnect target abort the pci 6520 controls these terminations using various methods, depending on the type of transaction performed. table 8-7. p_serr# assertion requirements in response to master abort on posted write description bit received master abort pcisr[13]=1; pci:06h p_serr# enable pcicr[8]=1; pci:04h master abort on posted write pserred[4]=0; pci:64h
section 8 pci bus operation conventional pci mode transaction termination pci 6520cb data book, version 2.0 8-14 preliminary ? 2004 plx technology, inc. all rights reserved. 8.6.3.1 posted write target termination response when the pci 6520 initiates a posted write transaction, the target termination cannot be returned to the initiator. table 8-8 delineates the response to each type of target termination that occurs during a posted write transaction. when a target retry or disconnect is returned and posted write data associated with that transaction remains in the write buffers, the pci 6520 initiates another write transaction to attempt to deliver the remaining write data. in the case of a target retry, the same address is driven as for the initial write transaction attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction attempt is updated to reflect the current dword address. if the initial write transaction is a memory write and invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, the pci 6520 uses the memory write command to deliver the remaining write data because less than a cache line is transferred in the subsequent write transaction attempt. after the pci 6520 makes 2 24 write attempts and fails to deliver all posted write data associated with that transaction, the pci 6520 asserts p_serr#, if enabled in the command register, and the device-specific p_serr# disable bit for this condition is not set. (refer to table 8-9.) the write data is discarded. table 8-8. response to post ed write target termination target termination response normal no additional action. target retry repeats write transaction to target. target abort sets target interface status register received target abort bit (primary?pcisr[12]=1; pci:06h, secondary?pcissr[12]=1; pci:1eh). asserts p_serr#, if enabled, and sets the primary status register signaled system error bit (pcicr[8]=1; pci:04h and pcisr[14]=1; pci:06h, respectively). table 8-9. p_serr# assertion requirements in response to posted write parity error description bit p_serr# enable pcicr[8]=0; pci:04h posted write parity error pserred[1]=0; pci:64h
section 8 conventional pci mode transaction termination pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-15 8?pci bus operation 8.6.3.2 delayed write target termination response when the pci 6520 initiates a delayed write transaction, the type of target termination received from the target can be returned to the initiator. table 8-10 delineates the response to each type of target termination that occurs during a delayed write transaction. the pci 6520 repeats a delayed write transaction until the pci 6520: completes at least one data transfer receives a master abort receives a target abort the pci 6520 makes 2 24 write attempts (default), resulting in a response of target retry. after the pci 6520 makes 2 24 attempts of the same delayed write transaction on the target bus, the pci 6520 asserts p_serr# if the command register p_serr# enable bit is set and the implementation-specific p_serr# disable bit for this condition is not set. (refer to table 8-11.) the pci 6520 stops initiating transactions in response to that delayed write transaction and the delayed write request is discarded. upon a subsequent write transaction attempt by the initiator, the pci 6520 returns a target abort. table 8-10. response to delayed write target termination target termination response normal returns disconnect to initiator with first data transfer only if multiple data phases are requested. target retry returns target retry to initiator. continue write attempts to target. target disconnect returns disconnec t to initiator with first data transfer only if multiple data phases are requested. target abort returns target abort to initiator. sets target interface status r egister received target abort bit. sets initiator interface status register signaled target abort bit. initiator (primary bus) target (secondary bus) initiator (secondary bus) target (primary bus) pcisr[11]=1; pci:06h pcissr[12]=1; pci:1eh pcisr[12]=1; pci:06h pcissr[11]=1; pci:1eh table 8-11. p_serr# assertion requirements in response to delayed write description bit p_serr# enable pcicr[8]=1; pci:04h delayed configuration or i/o write non-delivery pserred[5]=0; pci:64h
section 8 pci bus operation conventional pci mode transaction termination pci 6520cb data book, version 2.0 8-16 preliminary ? 2004 plx technology, inc. all rights reserved. 8.6.3.3 delayed read target termination response when the pci 6520 initiates a delayed read transaction, the abnormal target responses can be returned to the initiator. other target responses depend on the amount of data the initiator requests. table 8-12 delineates the response to each type of target termination that occurs during a delayed read transaction. the pci 6520 repeats a delayed read transaction until the pci 6520: completes at least one data transfer receives a master abort receives a target abort produces 2 24 read attempts, resulting in a response of target retry after the pci 6520 produces 2 24 attempts of the same delayed read transaction on the target bus, the pci 6520 asserts p_serr# if the command register p_serr# enable bit is set and the implementation-specific p_serr# disable bit for this condition is not set. (refer to table 8-13.) the pci 6520 stops initiating transactions in response to that delayed read transaction, and the delayed read request is discarded. upon a subsequent read transaction attempt by the initiator, the pci 6520 returns a target abort. table 8-12. response to delayed read target termination target termination response normal if prefetchable, target disconnects only if initiator reques ts more data than read from target. if non-prefetchable, target disconnects on first data phase. target retry re-initiates read transaction to target. target disconnect if initiator requests more data than r ead from target, returns target disconnect to initiator. target abort returns target abort to initiator. sets target interface status r egister received target abort bit. sets initiator interface status register signaled target abort bit. initiator (primary bus) target (secondary bus) initiator (secondary bus) target (primary bus) pcisr[11]=1; pci:06h pcissr[12]=1; pci:1eh pcisr[12]=1; pci:06h pcissr[11]=1; pci:1eh table 8-13. p_serr# assertion requirements in response to delayed read description bit p_serr# enable pcicr[8]=1; pci:04 delayed read-no data from target pserred[6]=0; pci:64h
section 8 conventional pci mode transaction termination pci bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 8-17 8?pci bus operation 8.6.4 pci 6520-initiated target termination the pci 6520 can return a target retry, disconnect, or abort to an initiator for reasons other than detection of that condition at the target interface. 8.6.4.1 target retry when it cannot accept write data or return read data as a result of internal conditions, the pci 6520 returns a target retry to the initiator when any of the following conditions are met: delayed write transactions transaction is in the process of entering the delayed transaction queue. transaction has entered the delayed transaction queue, but target response has not been received. target response was received, but the posted memory write ordering rule prevents the cycle from completing. delayed transaction queue is full; therefore, transaction cannot be queued. transaction with the same address and command was queued. locked sequence is being propagated across the pci 6520, and the write transaction is not a locked transaction. target bus is locked and the write transaction is a locked transaction. delayed read transactions transaction is in the process of entering the delayed transaction queue. read request was queued, but read data is not yet available. data was read from the target, but the data is not at the head of the read data queue, or a posted write transaction precedes it. delayed transaction queue is full, and the transaction cannot be queued. delayed read request with the same address and bus command was queued. locked sequence is being propagated across the pci 6520, and the read transaction is not a locked transaction. target bus is locked and the read transaction is a locked transaction. posted write transactions posted write data buffer does not contain sufficient space for the address and at least two qwords of write data. locked sequence is being propagated across the pci 6520, and the write transaction is not a locked transaction. when a target retry is returned to a delayed transaction initiator, the initiator must repeat the transaction with the same address and bus command, as well as the data if this is a write transaction, within the time frame specified by the master timeout value; otherwise, the transaction is discarded from the buffers.
section 8 pci bus operation conventional pci mode transaction termination pci 6520cb data book, version 2.0 8-18 preliminary ? 2004 plx technology, inc. all rights reserved. 8.6.4.2 target disconnect the pci 6520 returns a target disconnect to an initiator when the pci 6520: reaches an internal address boundary reaches a 4-kb boundary for a posted memory write cycle cannot accept further write data contains no further read data to deliver 8.6.4.3 target abort the pci 6520 returns a target abort to an initiator when the pci 6520: returns a target abort from the intended target detects a master abort on the target, and the master abort mode bit is set (bcntrl[5]=1; pci:3eh) cannot obtain delayed read data from the target nor deliver delayed write data to the target after 2 24 attempts when returning a target abort to the initiator, the pci 6520 sets the status register signaled target abort bit corresponding to the initiator interface (pcisr[12 or 11]=1; pci:06h).
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-1 9?pci-x bus operation 9 pci-x bus operation this section describes pci-x transactions that the pci 6520 responds to as a target and those it initiates as a master when operating with one or both of its interfaces in pci-x mode. 9.1 overview because the pci 6520 is a pci-x bridge (capable of operating in pci-x mode), each of the pci 6520 interfaces (primary or secondary) is capable of operating in conventional pci mode when a conventional pci device is installed (pci-xcap is connected to ground). the pci 6520 supports pci-x mode in the following way: source bridge for the primary bus informs the pci 6520 of the primary bus mode, with the pci-x initialization pattern at the rising edge of p_rstin# senses s_xcap_in state and properly initializes the secondary bus devices supports 64-bit addressing on both interfaces implements a 64-bit ad bus on either interface completes all dword and burst memory read transactions as split transactions, if the transactions cross the pci 6520 and the originating interface is in pci-x mode pci 6520 does not support system topologies, special cycle, and interrupt acknowledge cases (in conventional pci nor pci-x mode) 9.2 general bus rules when operating in pci-x mode, the pci 6520 adheres to the following pci-x transactions rules: address phase is the phase in which frame# is asserted. in the address phase, the ad bus contains the starting address ( except for split completions) and the cbe bus contains the command. starting address of configuration read and write transactions is aligned to a dword boundary. split completion transactions use only a partial starting address. attribute phase follows the address phase(s). in the target response phase, the cbe bus is reserved and driven high (the clock after the attribute phase). burst transactions include the byte count (number of bytes between the first byte of the transaction and the last byte of the sequence, inclusive) in the attributes. dword transactions do not use a byte count and reserve the attribute byte count field. target response phase is one or more clocks after the attribute phase and ends when the target asserts devsel#. if no target asserts devsel#, there are no data phases (master abort). transactions using the i/o read and write and configuration read and write commands (one data phase transaction) are initiated only as 32-bit transactions (req64# is de-asserted, as in conventional pci mode). for memory write transactions, the byte count is not adjusted for bytes whose byte enables are de-asserted within the transaction (byte count is the same). table 9-1 lists the definitions for typical conventional pci (provided for reference) and pci-x transaction phases.
section 9 pci-x bus operation general bus rules pci 6520cb data book, version 2.0 9-2 preliminary ? 2004 plx technology, inc. all rights reserved. table 9-1. transaction phase definitions conventional pci transaction phases description pci-x transaction phases description address one clock for sac. two clocks for dac. address one clock for sac. two clocks for dac. data clocks (after the address phase) in which data transfer is allowed. attribute one clock. provides further details about the transaction. initiator termination initiator signals the end of the transaction on the last data phase. target response one or more clocks when the target claims the transaction by asserting devsel#. turn-around idle clock for changing from one signal driver to another. data clocks in which data transfer is allowed. initiator termination initiator signals the end of the transaction one clock before the last data phase. turn-around idle clock for changing from one signal driver to another.
section 9 general bus rules pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-3 9?pci-x bus operation 9.2.1 initiator rules when operating in pci-x mode, the pci 6520 adheres to the following rules when initiating a transaction: begins a transaction by asserting frame# within two clocks after gnt# is asserted and the bus is idle (within six clocks if the transaction uses a configuration command). asserts irdy# two clocks after the attribute phase (in pci-x, wait states are not allowed for initiators). de-asserts frame# one clock before the last data phase (for four or more data phases) or two clocks after the target asserts trdy# for a single data phase (or terminates the transaction with another method). de-asserts irdy# one clock after the last data phase (for four or more data phases) or two clocks after the target asserts trdy# for a single data phase (or terminates the transaction with another method). ends the transaction as a master abort if no target asserts devsel# on or before the sub decode time. for write and split completion transactions, the pci 6520 drives the first data value on the ad bus two clocks after the attribute phase and advances to the second data value (for burst transactions with more than one data phase) two clocks after the target asserts devsel# (in anticipation of the target asserting trdy#). if the target inserts wait states (by not asserting trdy# after devsel# assertion), the pci 6520 toggles between the first and second data values until the target asserts trdy# (or terminates the transaction with another method). terminates a transaction when the byte count is satisfied. disconnects a burst transaction (before the byte count is satisfied) only on an adb. pci 6520 retains 64 clocks of latency timer value, and disconnects the current transaction on the next adb if the latency timer expires and gnt# is de-asserted. 9.2.2 target rules when operating in pci-x mode, the pci 6520 adheres to the following rules when responding to a transaction as a target: memory address range for the pci 6520 (and all devices) is no smaller than 128 bytes and aligned to adbs. claims the transaction by asserting devsel#, using decode b. does not signal wait state after the first data phase. signals split response, target abort, or retry within eight clocks of frame# assertion and signals single data phase disconnect (on the first data phase only), data transfer, or disconnect at the next adb within 16 clocks of frame# assertion. may signal target abort on any data phase, regardless of its relationship to an adb. if devsel#, stop#, and trdy# are not de-asserted, the pci 6520 de-asserts these signals one clock after the last data phase, then floats them one clock after that. 9.2.3 bus arbitration rules the following are the bus arbitration rules: pci 6520 asserts and de-asserts req# on any clock (no requirement to de-assert req# after a target termination). pci 6520 de-asserts req# on any clock, independent of whether gnt x # is asserted (without transaction initiation after gnt x # assertion). arbiter asserts gnt x # on any clock if all the gnt x # signals are de-asserted. gnt x # remain asserted for a minimum of five clocks while the bus is idle or until the initiator asserts frame# or de-asserts req#. if only one device asserts req#, the arbiter holds gnt x # asserted to that device. if the arbiter de-asserts gnt x # to one device, it must wait until the next clock to assert gnt x # to another device. fast back-to-back transactions are not allowed in pci-x mode.
section 9 pci-x bus operation pci-x sequences pci 6520cb data book, version 2.0 9-4 preliminary ? 2004 plx technology, inc. all rights reserved. 9.2.4 configuration transaction rules when operating in pci-x mode: initiators must drive the address for four clocks before asserting frame# transaction must include the target device number in ad[15:11] of the address phase type 0 configuration write transaction target stores its device and bus numbers in its internal registers 9.2.5 parity error rules in pci-x mode, when the pci 6520 detects a data parity error while receiving data ( for example , the target of a write or split completion, or initiator of a read), the pci 6520 asserts perr# on the second clock after par and par64 are driven (one clock later than conventional pci mode). during read transactions, as a target, the pci 6520 drives par and par64 on clock n+1 for the read data it drives on clock n and the byte enables driven by the initiator on clock n+1 . during write transactions, as an initiator, the pci 6520 drives par and par64 on clock n+1 for the write data and byte enables it drives on clock n . pci 6520 asserts serr# when it detects a parity error during an attribute phase. 9.2.6 bus data width rules in pci-x mode, the bus data width of each transaction is determined with a handshake protocol (similar to conventional pci protocol) on ack64# and req64# pci 6520 implements 64-bit in both its interfaces and is capable of generating a 64-bit memory address attribute phase is always a single clock long for both 64- and 32-bit initiators only burst transactions (memory commands other than memory read dword) use 64-bit data transfers 9.2.7 split transaction rules transactions that are terminated with split response result in one or more split completion transactions split completions contain read data or a split completion message, but not both if returning read data, the completer must return all data (the full byte count) unless an error occurs requester must accept all split completion data phases, and can terminate a split completion with data transfer or target abort if the request is a write transaction, or if the completer encounters an error while executing the request, the completer sends a split completion message to the requester 9.3 pci-x sequences one or more transactions of a single logical transfer is called a sequence . if a sequence is broken into more than one transaction, the bytes of all these transactions are included in the request byte count that started the sequence. each transaction in the same sequence carries the same requester id and tag. the pci 6520 does not initiate a new sequence using the same tag until the previous sequence using that tag is complete. the sequence has more than one transaction if it is a burst write and disconnected by the initiator or target. the initiator must resume the sequence by initiating another burst write transaction, using the same command and adjusting the starting address and data byte count. if the sequence is a burst write and the target signals a target abort or no target responds (master abort), the sequence ends when the transaction terminates. if the sequence is a burst read that executes as an immediate transaction, the sequence terminates when the transaction terminates. the requester is not required to resume an immediate read sequence. when a sequence crosses the pci 6520, the number of transactions within the sequence on each bus is determined by the device behavior on each bus. the pci 6520 maintains split completions, in address order, for the same sequence.
section 9 adb and buffer size pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-5 9?pci-x bus operation 9.4 adb and buffer size an allowable disconnect boundary (adb) is an aligned 128-byte address [the lower seven bits are zeros (0)]. adbs are the same, regardless of transaction width. to proceed from one adb to the next, a burst transaction requires 16 data phases on a 64-bit bus and 32 data phases on a 32-bit bus. after a burst data transfer starts and the target accepts more than a single data phase, the transaction can only be stopped using one of the following methods: target or initiator disconnect at an adb transaction byte count is satisfied target abort if a burst transaction is disconnected (by the initiator or target) on an adb, the last byte address transferred is 7fh (modulo 80h). 9.5 dependencies between ad and cbe buses pci-x memory, i/o, and configuration spaces are addressable at the byte level as conventional pci mode. bytes appear on byte lanes according to their individual byte address and transfer width, as listed in table 9-2. for burst transactions, the pci-x requester uses the full address bus to indicate the starting byte address (including ad[1:0]) and includes the attribute byte count field. for i/o and memory dword transactions, the pci-x initiator uses the full address bus to indicate the starting address (including ad[1:0]). the attribute byte count field is reserved . the ending address is always the last byte of the dword. note: interrupt acknowledge and special cycle transactions have no address. the cbe bus is reserved and driven high throughout burst transactions ( except memory writes). during the data phases of all dword and memory write transactions, the cbe bus is used as byte enables. table 9-2. byte lane assignments byte lane transfer width byte address ad[2:0] 32-bit 64-bit 000b 0 0 001b 1 1 010b 2 2 011b 3 3 100b 0 4 101b 1 5 110b 2 6 111b 3 7
section 9 pci-x bus operation pci-x command encoding pci 6520cb data book, version 2.0 9-6 preliminary ? 2004 plx technology, inc. all rights reserved. 9.6 pci-x command encoding pci-x command codes are listed in table 9-3. the initiator must not generate reserved commands and targets should ignore transactions using reserved commands. for all commands ( except dac), the transaction command appears on cbe[3:0]# during the single address phase. for transaction with dacs, cbe[3:0]# contains the dac command in the first address phase and the transaction command in the second address phase. the alias to memory read and write block commands are not generated by the initiators, and are treated as memory read block and memory write block, respectively, by targets. for 64-bit transactions, cbe[7:4]# contain the transaction command in both address phases. table 9-3. pci-x command encoding cbe[3:0]# pci-x command length byte enable usage 0000b interrupt acknowledge (not supported) dword valid 0001b special cycle (not supported) dword valid 0010b i/o read dword valid 0011b i/o write dword valid 0100b reserved n/a n/a 0101b reserved n/a n/a 0110b memory read dword dword valid 0111b memory write burst valid 1000b alias to memory read block burst reserved / driven high 1001b alias to memory write block burst reserved / driven high 1010b configuration read dword valid 1011b configuration write dword valid 1100b split completion burst reserved / driven high 1101b dac n/a n/a 1110b memory read block burst reserved / driven high 1111b memory write block burst reserved / driven high
section 9 attributes pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-7 9?pci-x bus operation 9.7 attributes the transaction is further defined by additional information included in the attribute phase (always single clock, regardless of the address or data transfer width). the upper buses (ad[63:32] and cbe[7:4]#) of 64-bit devices are reserved and driven high during the attribute phase. pci-x transactions have three attribute formats. the requester attribute format applies to all transactions, except type 0 configuration read and write transactions and split completion transactions. figure 9-1 illustrates the requester attribute bit assignments. the requester id (ad[23:8]) is the combination of the requester bus, device, and function numbers. the sequence id (ad[28:8]) is the combination of the requester id and tag. table 9-4 lists the requester attribute bit definitions.
section 9 pci-x bus operation attributes pci 6520cb data book, version 2.0 9-8 preliminary ? 2004 plx technology, inc. all rights reserved. figure 9-1. requester attribute bit assignments 35 32 31 30 29 28 24 23 16 15 11 10 8 7 0 upper byte count r ns ro tag requester bus number requester device number requester function number lower byte count cbe[3:0]# ad[31:0] table 9-4. requester attribute bit definitions bit(s) attribute function cbe[3:0]# ad[7:0] upper byte count lower byte count example : byte count[11:0] bytes 0000_0000_0001b 1 0010_0101_0110b 598 1111_1111_1111b 4095 0000_0000_0000b 4096 indicates the number of bytes the initiator plans to move in the remainder of the sequence. if the transaction is disconnected for any reason and the initiator continues the sequence, the initiator must adjust the byte count contents in the subsequent transacti ons of the same sequence to be the number of bytes remaining in the sequence. ad[10:8] requester function number contains the requester function number (the function in the configuration address to which the function responds). ad[15:11] requester device number contains the device number assigned to the requester (from the pci-x bridge status register device number bits, pcixbsr[7:3]; pci:f4h). ad[23:16] requester bus number identifies the requester bus number (from the pci-x bridge status register bus number bits, pcixbsr[15:8]; pci:f4h). ad[28:24] tag uniquely identifies up to 32 sequences from a single initiator. the initiator assigns a unique tag to each sequence that begins before the previous one ends. tag identifies the appropriate split completion transaction. ad29 relaxed ordering attribute (ro) devices are allowed to set ad29 to load sequences and must clear it for control and status sequences. split read requesters are unaffected by this bit. ad30 no snoop (ns) if an initiator sets ad30, the initiator guarantees that the locations between the starting and ending address, inclusive, of this sequence are not stored in a system cache. if a write transaction is disconnected, the initiator must not change this attribute on a subsequent transaction in the same sequence if an immediate read transaction disconnects, the sequence ends pci 6520 ignores ad30 and forwards it, unmodified, with the transaction. ad31 reserved (r) set to 0 by the requester and ignored by the completer.
section 9 burst transactions pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-9 9?pci-x bus operation 9.8 burst transactions a burst transaction is a transaction that uses one of the following commands: burst write transactions ?memory write, memory write block, or alias to memory write block burst read transactions ?memory read block or alias to memory read block commands split completion burst transactions (may be initiated as 64- or 32-bit) transfer data on one or more data phase, up to that required to satisfy the maximum byte count. burst transactions use the full address bus (including ad[2:0]) to specify the transaction starting byte address. burst transactions can start on one side and end on the other of an adb, a memory page boundary, the first 4 gb memory address boundary and so forth. during burst transaction data phases, the cbe bus is reserved and driven high by the initiator for all transactions ( except memory writes). 9.8.1 burst write and split completion the pci 6520 executes burst write and split completion transactions as immediate transactions, as follows: as an initiator, the pci 6520 is the command source, address, attribute, and data. as a target, terminates a burst write transaction with target abort, single data phase disconnect, wait state, data transfer, retry, or disconnect at the next adb. pci 6520 terminates a split completion transaction with target abort, wait state, or data transfer, retry, or disconnect at the next adb. targets are not allowed to respond with split response. cbe bus is reserved and driven high after the address phase of all burst writes and split completion transactions ( except memory writes). all bytes between the starting and ending address, inclusive, are included in these transactions. if the target inserts initial wait states, it must do so in pairs of clocks, and the initiator must toggle between the first and second data patterns until the target begins accepting data. 9.8.2 burst read transactions burst read transactions use the memory read block or alias to memory read block commands. as an initiator, the pci 6520 is the source of the command, address, and attributes (the completer is the source of the data). as a target, the pci 6520 responds to a burst read transaction with split response, target abort, single data phase disconnect, wait state, data transfer, retry, or disconnect at the next adb. if the pci 6520 responds (as a target) by signaling single data phase disconnect, data transfer, or disconnect at the next adb, data transfers during the read transaction. if the pci 6520 responds (as a target) with a split response, no data transfers during the read transaction but is later transferred in one or more split completion transactions. 9.9 dword transactions a pci-x dword transaction uses interrupt acknowledge, special cycle, i/o read, i/o write, configuration read, configuration write, or memory read dword. the pci 6520 considers the following pci-x rules: dword transactions must be initiated as 32-bit transfers (req64# must be de-asserted and ad[63:32], cbe[7:4]#, and par64 are not used) dword transactions retain a single data phase and affect more than a single dword reserved attributes must be set to 0 by the initiator and ignored by the target byte enables are not valid until two clocks after the attribute phase, and pci-x completer with locations that exhibit read side effects must not start a read operation until the byte enables are valid interrupt acknowledge has no address, and drives any value on the ad[31:0] bus during the address phase
section 9 pci-x bus operation device select timing pci 6520cb data book, version 2.0 9-10 preliminary ? 2004 plx technology, inc. all rights reserved. 9.10 device select timing a pci-x target claims transactions by asserting devsel#, using one of the timings listed in table 9-5 (conventional pci mode devsel# timing is listed for reference). 9.11 wait states and target initial latency when initiating a transaction, the pci 6520 (and all pci-x initiators) does not insert wait states. the pci 6520: asserts irdy# two clocks after the attribute phase and drives write data on the ad bus or prepares to accept read data after irdy# is asserted, it continues to assert irdy# until the transaction ends when responding to a transaction, it (and all pci-x targets) inserts wait states inserts wait states (in pairs of clock for burst write and split completion transactions) only on the initial data phase for transactions of more than one data phase, it does not signal a wait state the target initial latency is measured from the clock in which the initiator asserts frame#, to the clock in which the target signals something other than a wait state. table 9-6 delineates the target initial latency for all devsel# timing combinations, number of address phases, and numbers of wait states. table 9-5. devsel# timing decode speed after address phase 1 1. decode speeds are measured from the second address phase in the case of dac. conventional pci pci-x 1 clock fast n/a 2 clocks medium decode a 3 clocks slow decode b 4 clocks sub decode c 5 clocks n/a n/a 6 clocks n/a sub 2 2. if no target asserts devsel# within the sub decode time, the initiator ends the transac tion as a master abort. after asserting devsel#, a target must complete the transaction with one or more data phases by signaling split response, target abort, single data phase disconnect, wait state, data transfer, retry, or disconnect at the next adb. the pci 6520 uses decode b timing.
section 9 split transactions pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-11 9?pci-x bus operation the maximum number of initial wait states a pci-x target is allowed to insert depends upon how the target terminates the transaction. target must signal split response, target abort, or retry within eight clocks of frame# assertion target must signal single data phase disconnect, data transfer, or disconnect at the next adb within 16 clocks of frame# assertion if large numbers of wait states are required, executing the transaction as a split transaction provides more efficient bus use on a read transaction, the target is allowed to insert any number of initial wait states up (need not be in pairs for read transactions) to the maximum number 9.12 split transactions targets must not assume that the pci 6520 (as an initiator) repeats a transaction terminated with retry. split transactions improve bus efficiency for transactions accessing targets that exhibit long latency. split transactions (in pci-x mode) replace delayed transactions (in conventional pci mode). a split transaction consists of at least two separate bus transactions?a requester-initiated split request, and one or more completer-initiated split completions. the following is the sequence of events that occurs for non-memory write transactions in which the initiator and target reside on opposite sides of the pci 6520 bridge. these transactions are memory read block, alias to memory read block, memory read dword, i/o read, i/o write, configuration read, or configuration write command. 1. split request (transaction terminated with a split response) occurs. 2. after signaling a split response, the pci 6520 forwards the transaction to the completer side. 3. completer terminates the transaction after immediate completion (abort) or split completion cycle. 4. pci 6520 initiates a split completion transaction to send the received read data or a split completion message to the requester. 5. pci 6520 becomes the initiator of the split completion transaction, and the requester becomes the target (the requester and pci 6520 switch roles). split completions for the same sequence must be initiated in address order. when the pci 6520 terminates a read transaction with split response, the pci 6520 transfers the entire requested byte count as a split completion. the pci 6520 provides four adqs of buffer space for the split completion. table 9-6. target initial latency wait states sac dac devsel# timing devsel# timing a b c sub a b c sub 034574568 145685679 2567967810 36781078911 4 7 8 9 11 8 9 10 12 5 8 910129101113 6 9 10 11 13 10 11 12 14 7 1011121411121315 8 1112131512131416 9 12131416131415n/a 10 13 14 15 n/a 14 15 16 n/a 11 14 15 16 n/a 15 16 n/a n/a 12 15 16 n/a n/a 16 n/a n/a n/a 13 16 n/a n/a n/a n/a n/a n/a n/a
section 9 pci-x bus operation split transactions pci 6520cb data book, version 2.0 9-12 preliminary ? 2004 plx technology, inc. all rights reserved. 9.12.1 split completion transaction a split completion transaction is a burst transaction (includes the byte count in the attribute phase) that uses the split completion command. the following are the characteristics of split completion cycles: cbe bus is reserved and driven high during all data phases split completion transactions can be initiated as 64- or 32-bit transfers target of a split completion is the requester that initiated the split request completer stores the requester id (bus, device, and function numbers) from the split request attribute phase requester id becomes part of the split completion address driven on the ad bus during the split completion address phase requester uses the requester id to recognize split completions that correspond to its split request split completion attributes carry information about the completer rather than the requester completer adjusts the address and byte count (to the portion remaining in the sequence) each time a split completion resumes completer can disconnect a split completion transaction only on an adb completer must maintain the split completion data in address order if the split request is a dword transaction, the lower address bits in the split completion address are set to 0h and the byte count bit in the completer attributes is set to 4h if the split request is a write transaction, a split completion message is driven on ad[31:0], regardless of the byte enables asserted in the split request if the split request is a read transaction, data is driven on ad[31:0] during the split completion data phase (only byte lanes corresponding to the byte enables in the split request contain valid data) 9.12.2 immediate completion by the completer when the pci 6520 forwards a split request, it expects that the completer immediately completes the transaction ( for example , executes the transaction as an immediate transaction rather than a split transaction) or for the transaction to end with a master abort. if the completer immediately completes the transaction, the pci 6520 creates a split completion transaction (split completion address and completer attributes) to return to the requester. split completions are created in the following way: pci 6520 creates the split completion address from the original request in the same way as a completer for the completer attributes, the pci 6520 creates the completer id for the bus in which the immediate completion occurred if the immediate completion occurred on the primary bus, the pci 6520 supplies the bus, device, and function numbers from the pci-x bridge status register (pcixbsr[15:0]; pci:f4h) if the immediate completion occurred on the secondary bus, the pci 6520 supplies the bus number from the secondary bus number register (pcisbno; pci:19h) and sets the device and function number bits to 0 (pcixbsr[7:0]=0h; pci:f4h) if the split request is a write transaction and the completer immediately completes it, the pci 6520 also creates a split completion message for the split completion data phase. 9.12.3 split completion address the split completion address is driven on the ad bus during the address phase of split completion transactions. (refer to figure 9-2.) the completer copies all information from the split request address and attribute phases. table 9-7 lists the split completion address bit definitions.
section 9 split transactions pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-13 9?pci-x bus operation figure 9-2. split completion address 3 0 31 30 29 28 24 23 16 15 11 10 8 7 6 0 bus command r ro tag requester bus number requester device number requester function number r lower address cbe[3:0]# ad[31:0] table 9-7. split completion address bit definitions bit(s) attribute function ad[6:0] lower address pci 6520 uses this information when forwarding a split completion to another bus operating in pci-x mode, to determine where the split completion starts relative to an adb. completer copies ad[6:0] from the least significant seven bits of the split request address, regardless of the command used by the split request, if: split request for this sequence was a burst read first split completion of the sequence split completion is not a split completion message ad[6:0] are set to 0h when the sequence resumes if: split completion is disconnected on an adb split request was a dword transaction split request was a split completion message ad7 reserved (r) set to 0 by the target initiator. ad[10:8] requester function number completer copies ad[10:8] from the corresponding bits of the requester attributes. the requester uses this information to identify the appropriate split completions. ad[15:11] requester device number completer copies ad[15:11] from the corresponding bits of the requester attributes. the requester uses this information to identify the appropriate split completions. ad[23:16] requester bus number completer copies ad[23:16] from the corresponding bits of the requester attributes. the requester uses this information to identify the appropriate split completions. pci 6520 uses this field to identify transactions to forward. ad[28:24] tag completer copies ad[28:24] from the corresponding bits of the requester attributes. the requester uses this information to identify the appropriate split completions. ad29 relaxed ordering attribute (ro) completer optionally copies ad29 from the corresponding bit of the requester attributes bridges throughout the system, using this bit to influence transaction ordering. ad[31:30] reserved (r) set to 00b by the requester and ignored by the completer. cbe[3:0]# bus command contains the split completion command.
section 9 pci-x bus operation split transactions pci 6520cb data book, version 2.0 9-14 preliminary ? 2004 plx technology, inc. all rights reserved. 9.12.4 completer attributes the attribute phase of a split completion contains the completer attributes (a combination of the completer id and information about the sequence stored from the split request). (refer to figure 9-3 and table 9-7.) figure 9-3. completer attribute bit assignments 35 32 31 30 29 28 24 23 16 15 11 10 8 7 0 upper byte count bcm sce scm r completer bus number completer device number completer function number lower byte count cbe[3:0]# ad[31:0] table 9-8. completer attribute bit definitions bit(s) attribute function cbe[3:0]# ad[7:0] upper byte count lower byte count example : byte count[11:0] bytes 0000_0000_0001b 1 0010_0101_0110b 598 1111_1111_1111b 4095 0000_0000_0000b 4096 indicates the number of bytes the initiator plans to move in this split completion. if the transaction is disconnected for any reason and the initiator continues the sequence, the initiator must adjust the byte count field contents in the subsequent transactions of the same sequence to be the number of bytes remaining in this sequence. if the split completion is a split completion message, the completer sets the byte count to four (0000_0000_0100b). ad[10:8] completer function number contains the function number (function in the configuration address to which the function responds) of the completer within the device. ad[15:11] completer device number contains the device number assigned to the completer (from the pci-x bridge status register device number bits, pcixbsr[7:3]; pci:f4h). ad[23:16] completer bus number identifies the requester?s bus number (from the pci-x bridge status register bus number bits, pcixbsr[15:8]; pci:f4h). ad[28:24] reserved (r) set to 0h by the requester and ignored by the completer. ad29 split completion message (scm) set to 0 by the completer if the split completion contains read data. set to 1 by the completer if the split completion contains a split completion message. ad30 split completion error (sce) set to 0 by the completer if the transaction is a split completion message that is an error message. ad31 byte count modified (bcm) set to 1 by the completer if the byte count bit for this split completion contains a number smaller than the full remaining transaction byte count (to disconnect the split completion at the first adb). set to 0 by the completer if the byte count bit contains the full remaining byte count of the split request, or if the split completion is a split completion message. note: the bcm bit is used only for split completions resulting from burst read transactions (memory read block and alias to memory read block) and is set to 0 for split completions resulting from all other commands.
section 9 split transactions pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-15 9?pci-x bus operation 9.12.5 split completion acceptance requirement the pci 6520 accepts all split completions resulting from its own split requests. the pci 6520 asserts devsel# on all split completions in which the sequence id (requester id and tag) corresponds to a pci 6520-issued split request. if the split completion requester id is corrupt, it is possible that the id matches that of an actual system device. the pci 6520 does not assert devsel# ( for example , ignores the corrupt transaction) if the requester id matches that of the pci 6520, but the tag does not match any outstanding requests from the pci 6520. when the pci 6520 asserts devsel# for a split completion, it accepts the entire byte count requested without signaling split response or single data phase disconnect. if the pci 6520 is executing one split transaction from one interface (issued split response on that interface), the pci 6520 terminates with retry unposted transactions on that interface until the previous split transaction completes. 9.12.6 split completion messages split completion transactions include a message if the completer attributes scm bit is set (ad29=1). a split completion message is a single dword burst transaction. the remaining lower address bits in the split completion address are set to 0 and the completer attributes byte count is set to 4h for all split completion messages. (refer to table 9-9.) the cbe bus is reserved and driven high during the data phase of a split completion message. the following illustrates the functions of split completion messages: notifies the requester when a split write request (i/o or configuration) has completed. indicates error conditions in which delivery of data for a read request or execution of a write request is not possible. terminates a sequence, regardless of the amount of bytes remaining to be sent. split completion message byte count bit indicates the number of bytes that were not sent for this sequence (if the split request was a burst read). the remaining lower address bits indicate the lower seven bits of the starting address of the remainder of the sequence. (refer to figure 9-4, table 9-9 and table 9-10 for further details.)
section 9 pci-x bus operation split transactions pci 6520cb data book, version 2.0 9-16 preliminary ? 2004 plx technology, inc. all rights reserved. figure 9-4. split completion message attribute bit assignments 31 28 27 20 19 18 12 11 8 7 0 message class message index r remaining lower address upper remaining byte count lower remaining byte count ad[31:0] table 9-9. split completion message bit definitions bit(s) attribute function ad[11:0] upper and lower remaining byte count if the split request was a burst memory read, the completer sets this field to the number of bytes of read data that were not sent. if the split request was a dword transaction, the completer sets ad[11:0] to 4h. ad[18:12] remaining lower address if the split request was a burst memory read, this field contains the least significant seven bits of the address of the first byte of read data that was not sent. if the split request was a dword transaction, the completer sets ad[18:12] to 0h. ad19 reserved (r) set to 0 by the requester and ignored by the completer. ad[27:20] message index identifies the type of message within the message class. (refer to table 9-10 for further details.) ad[31:28] message class split completion messages classes. (refer to table 9-10 for further details.) class values: 0000b = write completion 0001b = pci-x bridge error 0010b = completer error 0011b ? 1111b = reserved note: the write completion class is used for split write completion messages. the remaining lower address bits are set to 0 (ad[18:12]=0h) and the upper and lower remaining byte count bits are set to 4h (ad[11:0]=4h) in the data phase of this split completion message.
section 9 split transactions pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-17 9?pci-x bus operation table 9-10. pci 6520 error message indices index ad[27:20] message class 0 (ad[31:28] = 0000b) message class 1 (ad[31:28] = 0010b) message class 2 (ad[31:28] = 0010b) 00h normal write completion master abort. pci 6520 encountered a master abort on the destination bus. byte count out of range. completer uses this message if the sum of the split request address and the byte count exceed the completer address range (over device boundary). the completer initiates split completion transactions with read data up to the device boundary. 01h reserved target abort. pci 6520 encountered a target abort on the destination bus. split write data parity error. completer sends this message when a dword write transaction is terminated with split response and a data parity error detected. 02h reserved write data parity error. pci 6520 encountered a data parity error on an unposted write transaction on the destination bus. device-specific error. completer uses this message if it encounters an error that prevents execution of the split request, and the error is not indicated by one of the other error messages. the pci 6520 encodes specific error or diagnostic information from the lower four bits of this index. 03h ? ffh reserved
section 9 pci-x bus operation pci-x mode transaction termination pci 6520cb data book, version 2.0 9-18 preliminary ? 2004 plx technology, inc. all rights reserved. 9.13 pci-x mode transaction termination the pci 6520 terminates a transaction using the following methods: initiator termination ?byte count disconnection or satisfaction master abort termination ?target termination, disconnection, or retry; split response; or target abort termination 9.13.1 pci 6520 initiator termination 9.13.1.1 byte c ount disconnection or satisfaction pci 6520 disconnection on an adb (before the byte count is satisfied), and pci 6520 termination at the end of the byte count, appear the same on the bus. pci 6520 termination in less than four data phases occurs only if the starting address, byte count, and bus data width are such that the transaction has fewer than four data phases when the pci 6520 intends to disconnect a transaction on the first adb, and the bus data width is such that the starting address is less than four data phases from the adb, the pci 6520 adjusts the byte count to terminate on that adb 9.13.1.2 pci 6520 master abort termination as an initiator, the pci 6520 de-asserts frame# and irdy# eight clocks after the address phase(s) if no target asserts devsel# within six clocks after the address phase(s). 9.13.2 pci 6520 target termination as a target, after the pci 6520 asserts devsel# in the target response phase, the pci 6520 completes the transaction with one or more data phases. on each clock after the target response phase, the pci 6520 signals its intention with a combination of target control signals (devsel#, stop#, and trdy#). a data phase ends each time the pci 6520 signals anything other than wait state. table 9-11 delineates the alternatives for data phase signaling. after the pci 6520 signals a data transfer on one data phase, the transaction continues until the byte count is satisfied or the initiator terminates the transaction. (when the pci 6520 signals a split response or retry, the transaction immediately terminates, although the byte count is not satisfied.) the transaction immediately terminates if the pci 6520 signals a split response or retry. following the transaction termination, the pci 6520 de-asserts devsel#, stop#, and trdy# one clock after the last data phase (if these signals are not currently de-asserted).
section 9 pci-x mode transaction termination pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-19 9?pci-x bus operation table 9-11. pci 6520 data phase signaling devsel# stop# trdy# data phase signaling data transfer transaction status de-asserted de-asserted de-asserted no response: master abort 1 1. pci 6520 does not allow this after asserting devsel#. no terminates de-asserted de-asserted asserted split response yes/no 2 2. no data transfer on a split response for a read transaction. the target latches data on a split response for a write transaction. in both cases, the transaction is not complete until the requester receives the split completion. terminates de-asserted asserted de-asserted target abort no terminates de-asserted asserted asserted single data phase disconnect yes terminates asserted de-asserted de-asserted wait state 3 3. wait states are allowed only on the first data phase. no continues asserted de-asserted asserted data transfer yes continues asserted asserted de-asserted retry no terminates asserted asserted asserted disconnect at next adb yes continues to an adb
section 9 pci-x bus operation pci-x mode bus and da ta transfer width pci 6520cb data book, version 2.0 9-20 preliminary ? 2004 plx technology, inc. all rights reserved. 9.13.2.1 pci 652 0 disconnects at next adb the pci 6520 signals a transaction disconnection at the next adb by asserting trdy#, stop#, and devsel# on any data phase of the transaction. after signaling disconnect at the next adb, the pci 6520 can signal only target abort on all subsequent data phases until the transaction ends. if the pci 6520 signals disconnect at the next adb: four or more data phases before an adb, the initiator disconnects the transaction on that adb after signaling a data transfer on the first data phase, and the transaction starting address is less than four data phases from an adb, the transaction crosses that adb and continues to the next adb 9.13.2.2 pci 6520 retry termination the pci 6520 indicates that it is temporarily unable to complete the transaction by signaling retry (asserting stop# and devsel# and holding trdy# de-asserted on the first data phase) under the following conditions: initialization time after rising edge of rstin# did not elapse buffers for accepting memory write or split completion transactions are currently full with previous data the pci 6520 discards all state information related to a transaction terminated with retry. 9.13.2.3 pci 6520 split response termination the pci 6520 signals a split response if it has enqueued the transaction as a split request by asserting trdy#, de-asserting devsel#, and holding stop# de-asserted on the first data phase of the transaction. the pci 6520 drives all ad bus bits high during the clock in which it signals a split response of a read transaction. 9.14 pci-x mode bus and data transfer width the pci 6520 determines the bus data width to which it is attached by the req64# state at the rising edge of rstin#. pci-x devices are allowed to implement a 64- or 32-bit interface. addresses are driven in one or two clocks, depending on whether the transaction uses a memory command and the address is below the first 4-gb boundary. attributes are always driven in a single clock for 64- and 32-bit devices. as in conventional pci mode, the width of a pci-x data transfer is negotiated between the initiator and the target on each transaction, using req64# and ack64#. attributes: pci 6520 is capable of generating addresses greater than 4 gb (when initiating memory transactions) all pci 6520 prefetchable memory range registers are 64-bit registers split completions always have a single address phase for 64- and 32-bit initiators when executing a transaction with a dac for a 64-bit transaction, the pci 6520 drives the entire address (lower address on ad[31:0] and upper address on ad[63:32]) and both commands (dac on cbe[3:0]# and transaction command on cbe[7:4]#) during the initial address phase. on the following clock, the pci 6520 drives the upper address on ad[63:0] and the transaction command on cbe[7:0]#.
section 9 connecting conventional pci and pci-x interfaces pci-x bus operation pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 9-21 9?pci-x bus operation the following requirements are applied to all pci-x devices: pci-x devices support a status bit, indicating whether they are a 64- or 32-bit device. only burst transactions use 64-bit transfers. dword transactions use 32-bit transfers. adbs are unaffected by the data transfer width. a 32-bit device has twice as many data phases between two adbs. ad2 is 0 or 1, depending on the transaction starting byte address. if ad2 of the starting byte address is 1 (the starting address is in the upper 32 bits of the bus), the 64-bit initiator must drive the data on ad[63:0] and the byte enables on cbe[7:0]# of the first data phase. ad[63:32] and cbe[7:4]# are driven high during the transaction attribute phase from a 64-bit initiator. if the target concurrently asserts ack64# and devsel# (a 64-bit target), and the target inserts wait states, the initiator must toggle between the first and second qword data phases on ad[63:0] and byte enables on cbe[7:0]#. if the transaction starts on an odd dword, that dword and its byte enables must be copied to the lower half of the bus each time the first data phase repeats. if the target does not assert ack64# (and the target inserts wait states), the initiator must toggle between the first and second dword data phases of the transaction on ad[31:0] and byte enables on cbe[3:0]#. 9.15 connecting conventional pci and pci-x interfaces this section provides the pci 6520 translation of commands and protocol between conventional pci and pci-x interfaces. 9.15.1 conventional pci requester, pci-x completer table 9-12 summarizes the command translation requirements from a conventional pci transaction to a pci-x transaction. when the pci 6520 prefetches more than a single dword, it uses the memory read block command. if a memory read block command is used, the byte count is controlled by the pci 6520 prefetch algorithm. the pci 6520 buffer memory writes transactions from its conventional pci interface, and counts the number of bytes to be forwarded to the pci-x interface. when the pci 6520 forwards a transaction other than a memory write transaction: pci 6520 terminates the transaction on the originating bus with retry, stored the address, commands, and so forth, and enqueues a delayed request after the pci 6520 finishes the request on the destination bus, it enqueues a delayed completion pci 6520 follows delayed transaction rules on the requester side (conventional pci bus) and split transaction rules on the completer side (pci-x bus) table 9-12. conventional pci-to-pci-x command translation conventional pci command pci-x command i/o read i/o read i/o write i/o write configuration read configuration read configuration write configuration write memory read memory read dword or memory read block memory read line memory read block memory read multiple memory read block memory write memory write or memory write block memory write and invalidate memory write block
section 9 pci-x bus operation connecting conventional pci and pci-x interfaces pci 6520cb data book, version 2.0 9-22 preliminary ? 2004 plx technology, inc. all rights reserved. 9.15.2 pci-x requester, conventional pci completer table 9-13 summarizes the command translation requirements from a pci-x transaction to a conventional pci transaction. the pci 6520 translates a pci-x memory read block command into one of three conventional pci memory read commands, based on the byte count and starting address. if the: starting address and byte count are such that only one or fewer dwords are being read, the conventional pci transaction uses the memory read command pci-x transaction reads more than one dword, but does not cross a cache line boundary, the conventional pci transaction uses the memory read line commands pci-x transaction crosses a cache line boundary, the conventional pci transaction uses the memory read multiple command if pci-x memory write block command (or memory write command) byte enables are set and the command starts and ends on a cache line boundary, the pci 6520 translates the command to the memory write command on the conventional pci interface. when forwarding a transaction other than a memory write, the pci 6520: terminates the transaction on the originating bus with split response. after executing the transaction on the conventional pci interface, the pci 6520 creates the split completion to return to the pci-x requester. follows split transaction rules on the requester side (pci-x bus) and delayed transaction rules on the completer side (conventional pci bus). table 9-13. pci-x-to-conventional pci command translation pci-x command conventional pci command i/o read i/o read i/o write i/o write configuration read configuration read configuration write configuration write memory read dword memory read memory read block memory read, memory read line, or memory read multiple memory write memory write or memory write and invalidate memory write block memory write or memory write and invalidate
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 10-1 10?address decoding 10 address decoding this section describes address decoding, including address ranges, memory address decoding, isa mode, and vga and private device support. 10.1 overview the pci 6520 uses three address ranges to control i/o and memory transaction forwarding across the bridge. these address ranges are defined by base and limit address registers in configuration space. 10.2 address ranges the pci 6520 uses the following address ranges to determine which i/o and memory transactions are forwarded from the primary-to-secondary pci bus, and from the secondary-to-primary pci bus: one 32-bit i/o address range one 32-bit memory-mapped i/o (non-prefetchable memory) range one 64-bit prefetchable memory address range transaction addresses falling within these ranges are forwarded downstream from the primary-to-secondary pci bus. transaction addresses falling outside these ranges are forwarded upstream from the secondary-to-primary pci bus. 10.2.1 i/o address decoding the pci 6520 uses the following mechanisms, defined in configuration space, to specify the i/o address space for downstream and upstream forwarding: i/o base and limit address registers (base? pciiobar; pci:1ch and pciiobaru16; pci:30h, limit?pciiolmt; pci:1dh and pciiolmtu16; pci:32h) isa enable bit (bcntrl[2]; pci:3eh) vga enable bit (bcntrl[3]; pci:3eh) vga palette snoop enable bit (pcicr[5]; pci:04h) to enable downstream i/o transaction forwarding, the command register i/o space enable bit must be set (pcicr[0]=1; pci:04h). if the i/o space enable bit is not set, i/o transactions initiated on the primary bus are ignored. to enable upstream i/o transaction forwarding, the command register master enable bit must be set (pcicr[2]=1; pci:04h). if the master enable bit is not set, the pci 6520 ignores i/o and memory transactions initiated on the secondary bus. setting the master enable bit also allows upstream memory transaction forwarding. caution: if any configuration state affecting i/o transaction forwarding is changed by a configuration write operation on the primary bus when there are ongoing i/o transactions on the secondary bus, the pci 6520 response to the secondary bus i/o transactions is unpredictable. configure the i/o base and limit address registers, and isa enable, vga enable, and vga palette snoop enable bits before setting the i/o space enable and master enable bits, and subsequently change these registers only when the primary and secondary pci buses are idle. 10.2.1.1 i/o base and limit address registers the pci 6520 implements one set of i/o base and limit address registers in configuration space that define an i/o address range for downstream forwarding. the pci 6520 supports 32-bit i/o addressing, which allows i/o addresses downstream from the pci 6520 to be mapped anywhere in a 4-gb i/o address space. i/o transactions with addresses that fall inside the i/o base and limit register-defined range are forwarded downstream from the primary-to-secondary pci bus. i/o transactions with addresses that fall outside this range are forwarded upstream from the secondary-to-primary pci bus. the i/o range can be disabled by setting the i/o base address to a value greater than that of the i/o limit address. when the i/ o range is disabled, all i/o transactions are forwarded upstream (no i/o transactions are forwarded downstream). the i/o base register consists of an 8-bit field (pciiobar; pci:1ch) and a 16-bit field (pciiobaru16; pci:30h). the upper four bits of the 8-bit field define bits [15:12] of the i/o base address.
section 10 address decoding memory address decoding pci 6520cb data book, version 2.0 10-2 preliminary ? 2004 plx technology, inc. all rights reserved. the lower four read-only bits are hardcoded to 0001b to indicate 32-bit i/o addressing support. bits [11:0] of the base address are assumed to be 0h, which naturally aligns the base address to a 4-kb boundary with a minimum granularity of 4 kb. the 16 bits contained in the i/o base upper 16 bits register (pciiobaru16; pci:30h) define ad[31:16] of the i/o base address. all 16 bits are read/write. after a primary bus or chip reset, the i/o base address value is initialized to 0000_0001h. the i/o limit register consists of an 8-bit field (pciiolmt; pci:1dh) and a 16-bit field (pciiolmtu16; pci:32h). the upper four bits of the 8-bit field define bits [15:12] of the i/o limit address. the lower four read-only bits are hardcoded to 0001b to indicate 32-bit i/o addressing support. bits [11:0] of the limit address are assumed to be fffh, which naturally aligns the limit address to the top of a 4-kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register (pciiolmtu16; pci:32h) define ad[31:16] of the i/o limit address. all 16 bits are read/write. after a primary bus or chip reset, the i/o limit address value is reset to 0000_ 0fffh. note: write these registers with their appropriate values before setting the command register master or i/o space enable bit (pcicr[2 or 0]=1; pci:04h). 10.3 memory address decoding the pci 6520 has three mechanisms for defining memory address ranges for memory transaction forwarding: memory-mapped i/o base and limit address registers (pcimbar; pci:20h and pcimlmt; pci:22h, respectively) prefetchable memory base and limit address registers (base?pcipmbar; pci:24h and pcipmbaru32; pci:28h, limit?pcipmlmt; pci:26h and pcipmlmtu32; pci:2ch) vga mode (bcntrl[3]=1; pci:3eh) this subsection describes the first two mechanisms. vga mode is described in section 10.5.1. to enable downstream memory transaction forwarding, the command register memory space enable bit must be set (pcicr[1]=1; pci:04h). to enable upstream memory transaction forwarding, the command register master enable bit must be set (pcicr[2]=1; pci:04h). setting the master enable bit also enables upstream i/o transaction forwarding. caution: if any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus when there are ongoing memory transactions on the secondary bus, response to the secondary bus memory transactions is unpredictable. configure the memory-mapped i/o base and limit address registers, prefetchable memory base and limit address registers, and vga enable bit before setting the memory space enable and master enable bits, and subsequently change these registers only when the primary and secondary pci buses are idle.
section 10 memory address decoding address decoding pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 10-3 10?address decoding 10.3.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as non-prefetchable memory. the memory-mapped i/o base and limit address registers define an address range that the pci 6520 uses to determine when to forward memory commands. the pci 6520 forwards a memory transaction from the primary-to-secondary interface if the transaction address falls within the memory-mapped i/o address range. the pci 6520 ignores memory transactions initiated on the secondary interface that fall into this address range. transactions that fall outside this address range are ignored on the primary interface and forwarded upstream from the secondary interface (provided that the transactions do not fall into the prefetchable memory range, or are not forwarded downstream by the vga mechanism). the memory-mapped i/o address range supports only 32-bit addressing. p-to-p bridge r1.2 does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address range has a granularity and alignment of 1 mb and a maximum range of 4 gb. the memory-mapped i/o address range is defined by a 16-bit memory-mapped i/o base address register (bar) and a 16-bit memory-mapped i/o limit address register (pcimbar; pci:20h and pcimlmt; pci:22h, respectively). the upper 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lower four bits are hardcoded to 0h. the lower 20 bits of the memory-mapped i/o base address are assumed to be 0h, which results in a natural alignment to a 1-mb boundary. the lower 20 bits of the memory-mapped i/o limit address are assumed to be f_ffffh, which results in an alignment to the top of a 1-mb block. note: write the pcimbar and pcimlmt registers with their appropriate values before setting the command register memory space enable or master enable bit. to disable the memory-mapped i/o address range, write the memory-mapped i/o base address register with a value greater than that of the memory-mapped i/o limit address register. 10.3.2 prefetchable memory base and limit address registers locations accessed in the prefetchable memory address range must have true memory-like behavior and not exhibit side effects when read ( that is , extra reads to a prefetchable memory location must not have side effects). the pci 6520 prefetches for all types of memory read commands in this address space. the pci 6520 prefetchable memory base and limit address registers define an address range that the pci 6520 uses to determine when to forward memory transactions. the pci 6520 forwards a memory transaction from the primary-to-secondary interface, if the transaction address falls within the prefetchable memory address range. the pci 6520 ignores memory transactions initiated on the secondary interface that fall into this address range. the pci 6520 does not respond to transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that the transactions do not fall into the memory-mapped i/o address range, or are not forwarded by the vga mechanism). the pci 6520 prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the prefetchable memory base and limit addresses. for address comparison, a single address cycle (sac; 32-bit address) prefetchable memory transaction is treated as a 64-bit address transaction, where the upper 32 bits of the address are equal to 0h. this upper 32-bit value of 0h is compared to the prefetchable memory base and limit address upper 32 bits registers. the prefetchable memory base address upper 32 bits register must be 0h to pass sac transactions downstream. the prefetchable memory address range is defined by a 16-bit prefetchable memory base address register and a 16-bit prefetchable memory limit address register (pcipmbar; pci:24h and pcipmlmt; pci:26h, respectively). the upper 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lower four read-only bits are hardcoded to 1h, indicating 64-bit address support. the lower 20 bits of the prefetchable memory base address are assumed to be 0h, which results in a natural alignment to a 1-mb boundary. the lower
section 10 address decoding isa mode pci 6520cb data book, version 2.0 10-4 preliminary ? 2004 plx technology, inc. all rights reserved. 20 bits of the prefetchable memory limit address are assumed to be f_ffffh, which results in an alignment to the top of a 1-mb block. the maximum memory address range is 4 gb for 32-bit addressing, and 2 64 bytes for 64-bit addressing. note: write the pcipmbar and pcipmlmt registers with their appropriate values before setting the command register memory space enable or master enable bit. to disable the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. the entire base register value must be greater than the entire limit register value ( that is , the upper 32 bits must be considered). therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set to a value greater than that of the lower limit register; otherwise, the upper 32-bit base register must be greater than the upper 32-bit limit register. 10.4 isa mode the pci 6520 supports isa mode by providing the bridge control register isa enable bit in configuration space (bcntrl[2]=1; pci:3eh). isa mode modifies the pci 6520 response inside the i/o address range to support i/o space mapping in the presence of an isa bus in the system. this bit only affects the pci 6520 response when the following conditions are met: transaction falls inside the address range defined by the i/o base and limit address registers, and address also falls inside the first 64 kb of i/o space (address bits [31:16]=0h) when the isa enable bit is set, the pci 6520 does not forward downstream i/o transactions that address the upper 768 bytes of each aligned 1-kb block. only those transactions addressing the lower 256 bytes of an aligned 1-kb block inside the base and limit i/o address range are forwarded downstream. transactions above the 64-kb i/o address boundary are forwarded, as defined by the i/o base and limit register address range. additionally, if the isa enable bit is set, the pci 6520 forwards upstream those i/o transactions that address the upper 768 bytes of each aligned 1-kb block within the first 64 kb of i/o space. the command configuration register master enable bit must also be set (pcicr[2]=1; pci:04h) to enable upstream forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream if the transactions fall outside the i/o address range. when the isa enable bit is set, devices downstream of the pci 6520 can have i/o space mapped into the first 256 bytes of each 1-kb segment below the 64-kb boundary, or anywhere in i/o space above the 64-kb boundary. 10.5 vga support the pci 6520 provides two modes for vga support: vga mode, supporting vga-compatible addressing vga snoop mode, supporting vga palette forwarding 10.5.1 vga mode when a vga-compatible device exists downstream from the pci 6520, enable vga mode by setting the bridge control register vga enable bit (bcntrl[3]=1; pci:3eh). when operating in vga mode, the pci 6520 forwards downstream those transactions that address the vga frame buffer memory and vga i/o registers, regardless of the i/o base and limit address register values. the pci 6520 ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer resides in the memory address range?000a_0000h to 000b_ffffh. read transactions to frame buffer memory are treated as non-prefetchable. the pci 6520 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. the vga i/o addresses consist of i/o addresses 3b0h to 3bbh and 3c0h to 3dfh.
section 10 private device support address decoding pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 10-5 10?address decoding these i/o addresses are aliased every 1 kb throughout the first 64 kb of i/o space [ that is , address bits [15:10] are not decoded and can be any value, while address bits [31:16] must be all zeros (0)]. vga bios addresses starting at c_0000h are not decoded in vga mode. 10.5.2 vga snoop mode the pci 6520 provides vga snoop mode, allowing for vga palette write transactions to be forwarded downstream. this mode is used when a graphics device downstream from the pci 6520 must snoop or respond to vga palette write transactions. to enable the mode, set the command register vga palette snoop enable bit (pcicr[5]=1; pci:04h). the pci 6520 claims vga palette write transactions by asserting devsel# in vga snoop mode. when the vga palette snoop enable bit is set, the pci 6520 forwards downstream transactions with i/o addresses 3c6h, 3c8h, and 3c9h. these addresses are also forwarded as part of the previously described vga compatibility mode. again, address bits [15:10] are not decoded, while address bits [31:16] must be equal to 0h ( that is , these addresses are aliased every 1 kb throughout the first 64 kb of i/o space). note: if both the vga enable and vga palette snoop enable bits are set (bcntrl[3]=1 and pcicr[5]=1, respectively), the pci 6520 behaves as if only the vga enable bit is set. 10.6 private d evice support the pci 6520 can support pci devices that are not visible to primary port hosts or masters. these devices are referred to as private devices and occupy private memory space. by pulling up the prv_dev input pin to 1, the pci 6520 enables use of private memory space at power-up. the private memory range must be set up by driver software. the pci 6520 does not respond to accesses to this private memory range on the primary or secondary port. when prv_dev=1, in conjunction with the private memory range, secondary idsels using s_ad[23:16] are also re-routed to s_ad24. if s_ad24 is not connected to a pci device, type 1 accesses by the primary host to secondary pci devices using s_ad[23:16] as idsel are master aborted on the secondary port. the private device and memory enable bits (ccntrl[3:2]; pci:40h, respectively) are initialized by the prv_dev input pin state. however, software can change the values of these bits after reset.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 11-1 11?transaction ordering 11 transaction ordering this section describes transaction ordering in conventional pci and pci-x modes. 11.1 conventional pci transaction ordering this subsection describes the ordering rules that control conventional pci transaction forwarding across the pci 6520. to maintain data coherency and consistency, the pci 6520 complies with the ordering rules set forth in pci r2.3. for a detailed discussion of transaction ordering, refer to pci r2.3, appendix e. 11.1.1 transactions governed by ordering rules in conventional pci mode, ordering relationships are established for the following transaction classes that cross the pci 6520: posted write transactions (comprised of memory write, and memory write and invalidate, transactions) ?completed at the source before completing at the destination ( that is , data is written into intermediate data buffers before reaching the target). delayed write request transactions (comprised of i/o write and configuration write transactions) ?terminated by target retry on the initiator bus and queued in the delayed transaction queue. a delayed write transaction must complete on the target bus before completing on the initiator bus. delayed write completion transactions (comprised of i/o write and configuration write transactions) ?completed on the target bus, with the target response queued in the buffers. a delayed write completion transaction proceeds in the direction opposite to that of the original delayed write request ( that is , the transaction proceeds from target-to-initiator bus). delayed read request transactions (comprised of all memory read, i/o read, and configuration read transactions) ?terminated by target retry on the initiator bus and queued in the delayed transaction queue. delayed read completion transactions (comprised of all memory read, i/o read, and configuration read transactions) ?completed on the target bus, and the read data was queued in the read data buffers. a delayed read completion transaction proceeds in the direction opposite that of the original delayed read request ( that is , the transaction proceeds from target-to-initiator bus). the pci 6520 does not combine, merge, nor collapse write transactions: combine separate write transactions into a single write transaction ?this optimization is best implemented in the originating master. merge bytes on separate masked write transactions to the same dword address ? this optimization is also best implemented in the originating master. collapse sequential write transactions to the same address into a single write transaction ? pci r2.3 does not allow combining of transactions. 11.1.2 general ordering guidelines conventional pci-independent transactions on the primary and secondary buses have a relationship only when those transactions cross the pci 6520. the following general ordering guidelines govern transactions crossing the pci 6520: ordering relationship of a transaction, with respect to other transactions, is determined when the transaction completes ( that is , when a transaction ends with a termination other than target retry). requests terminated with a target retry can be accepted and completed in any order with respect to other transactions terminated with a target retry. if the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one completes. if more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction requests, using a fairness algorithm. repeating a delayed transaction cannot be contingent upon completion of another delayed transaction; otherwise, deadlock may occur.
section 11 transaction ordering conventional pci transaction ordering pci 6520cb data book, version 2.0 11-2 preliminary ? 2004 plx technology, inc. all rights reserved. write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. the pci 6520 can simultaneously accept posted write transactions on both interfaces, as well as simultaneously initiate posted write transactions on both interfaces. acceptance of a posted memory write transaction as a target can never be contingent on the completion of an unlocked, unposted transaction as a master. this is true of the pci 6520 and must also be true of other bus agents; otherwise, deadlock may occur. pci 6520 accepts posted write transactions, regardless of the state of completion of delayed transactions being forwarded across the pci 6520. 11.1.3 ordering rules the following ordering rules describe the transaction relationships. each ordering rule is followed by an explanation, and the ordering rules are referred to by number in table 11-1. these ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing the pci 6520 in the same direction. note that delayed completion transactions cross the pci 6520 in the direction opposite that of the corresponding delayed requests. 1. posted write ?posted write transactions must complete on the target bus in the order in which the transactions were received on the initiator bus. the subsequent posted write transaction could be setting a flag that covers the data in the first posted write transaction. if the second transaction were to complete before the first transaction, devices checking that flag could subsequently be using stale data. 2. delayed write request ?delayed write requests cannot pass previously queued posted write data. as in the case of posted memory write transactions, the delayed write transaction might be setting a flag regarding data in the posted write transaction. if the delayed write request were to complete before the earlier posted write transaction, devices checking the flag could subsequently be using stale data. 3. delayed read request ?delayed read requests traveling in the same direction as previously queued posted write transactions must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. the read transaction might be in the same location as the write data; therefore, if the read transaction were to pass the write transaction, the read would return stale data. 4. delayed write completion ?posted write transactions must be provided opportunities to pass delayed read and write requests and completions. otherwise, deadlock may occur when bridges that support delayed transactions are used in the same system with bridges that do not support delayed transactions. a fairness algorithm is used to arbitrate between the posted write and delayed transaction queues. the pci 6520 can return delayed read transactions in a different order than requested if the drt out-of-order enable bit is set to 1 (mscopt[2]=1; pci:46h). requested cycles can execute out of order across the bridge, if all other ordering rules are satisfied. therefore, if the pci 6520 starts a delayed transaction that is retried by the target, the pci 6520 can execute another transaction in the delayed transaction request queue. also, if there are delayed write and read requests in the queue, and the read data fifos are full, the pci 6520 may execute the delayed write request before the delayed read request. 5. delayed read completion ?delayed read completions must ?pull? ahead of previously queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the bridge as the target of the write transaction. the posted write transaction must complete on the target before read data is returned to the initiator. the read transaction could be to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete.
section 11 conventional pci transaction ordering transaction ordering pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 11-3 11?transaction ordering the pci 6520 can generate cycles across the bridge in the same order requested if the miscellaneous options register drt out-of-order enable bit is set (mscopt[2]=1; pci:46h). by default, requested cycles can execute out of order across the bridge if all other ordering rules are satisfied. therefore, if the pci 6520 begins a delayed transaction that is retried by the target, the pci 6520 can execute another transaction in the delayed transaction request queue. additionally, if there is both delayed write and delayed read requests in the queue, and the read data fifo is full, the pci 6520 may execute the delayed write request before the delayed read request. on cycle completion, the pci 6520 may complete cycles in a different order than that requested by the initiator. 11.1.4 data synchronization data synchronization refers to the relationship between interrupt signaling and data delivery. pci r2.3 provides the following alternative methods for synchronizing data and interrupts: device signaling the interrupt performs a read of the data just written (software) device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software) system hardware guarantees that write buffers are flushed before interrupts are forwarded the pci 6520 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. therefore, all posted write transactions must be followed by a read operation, from the pci 6520 to the location recently written (or some other location along the same path), or from the device driver to a pci 6520 register. table 11-1. conventional pci transaction ordering summary pass posted write delayed write request delayed read request delayed write completion delayed read completion posted write n 1 y 4 y 4 y 4 y 4 delayed write request n 5 yyyy delayed read request n 3 yyyy delayed write completion yyyyy delayed read completion n 2 yyyy legend : superscript number = refers to the five applicable ordering rules listed in section 11.1.3. many entries are not governed by these ordering rules; therefore, the implementation ca n choose whether the transactions pass each other. y = transactions may be completed out of order or ?pass? each other. n = row transaction must not pass the column transaction.
section 11 transaction ordering pci-x transaction ordering pci 6520cb data book, version 2.0 11-4 preliminary ? 2004 plx technology, inc. all rights reserved. 11.2 pci-x transaction ordering this subsection describes the ordering rules that control pci-x transaction forwarding across the pci 6520. for a detailed discussion of transaction ordering, refer to pci-x r1.0b, use of relaxed ordering appendix, chapter 11. pci-x introduces two features that affect transaction ordering and passing rules that are not present in conventional pci?relaxed ordering attribute bit and split transactions. 11.2.1 relaxed orde ring attribute bit the pci-x relaxed ordering attribute bit (ad29) may be used to allow a memory write transaction to pass other memory writes and to allow split read completions to pass memory writes. if the relaxed ordering attribute bit is set for a read transaction, the completion for that transaction is allowed to pass previously posted memory write transactions traveling in the direction of the completion. if the relaxed ordering attribute bit is set for a memory write transaction, that transaction is allowed to pass previous posted memory write transactions moving in the same direction on the host bridge. note: the pci 6520 ignores the relaxed ordering attribute bit for memory write transactions and maintains the order of memory write transactions that cross the pci 6520. 11.2.2 split transactions in pci-x, split transaction ordering and deadlock-avoidance rules are almost identical to the delayed transaction rules in conventional pci (transaction order is established as the transactions complete). table 11-2 lists the ordering requirements for all split and memory write transactions (the columns represent the first of two transactions, and the rows represent the second). table 11-3 provides a case-by-case discussion of split transactions. split requests can be reordered with respect to other split requests. if an initiator requires two split transactions to complete in order, the initiator must not issue the second request until the first split transaction completes. split read completions that have the same sequence id must remain in address order. the completer must supply the split read completions on the bus, in address order, to guarantee that the requester always receives the data in its natural order. there are no ordering restrictions for split read completions with different sequence ids.
section 11 pci-x transaction ordering transaction ordering pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 11-5 11?transaction ordering table 11-2. pci-x transaction ordering and deadlock-avoidance rules row pass column? memory write (column 2) split read request (column 3) split write request (column 4) split read completion (column 5) split write completion (column 6) memory write (row a) a) no b) y/n yes yes yes yes split read request (row b) no y/n y/n y/n y/n split write request (row c) no y/n y/n y/n y/n split read completion (row d) a) no b) y/n yes yes a) y/n b) no y/n split write completion (row e) y/n yes yes y/n y/n legend : yes = second transaction must be allowed to pass the first transaction to avoid deadlock. y/n = pci 6520 may optionally allow the second transaction to pass the first. no = second transaction must not be allowed to pass the first transaction (to preserve strong write ordering). note: refer to table 11-3 for a case-by-case discussion of the split transactions.
section 11 transaction ordering pci-x transaction ordering pci 6520cb data book, version 2.0 11-6 preliminary ? 2004 plx technology, inc. all rights reserved. table 11-3. pci-x split transactions?case-by-case discussion split transaction comments a2a unless the relaxed ordering attribute bit is set, a memo ry write transaction must not pass any other memory writes. a2b if the relaxed ordering attribute bit is set, that memory wr ite transaction is allowed to pass all other memory writes in the host bridge only. a3, a4 memory write transactions must be allowed to pass split requests to avoid deadlock. a5, a6 memory write transactions must be allowed to pass split completions to avoid deadlock. b2, c2 split requests cannot pass memory write transactions. b3, b4 split requests are allowed to be bl ocked by, or pass, split completions. c3, c4 split transactions have the same requirements as conventional pci delayed transactions. b5, b6 split requests are allowed to be bl ocked by, or pass, split completions. c5, c6 split requests pass split completions. (deadlock does not occur if split completions block split requests.) d2a unless the relaxed ordering attribute bit is set, split read completions cannot pass memory writes. d2b if the relaxed ordering attribute bit is set, split read completions are allowed to pass previous posted memory write transactions. d3, d4 split read completions must be allowed to pass all split requests to avoid deadlock. d5a unless two split read completions are part of the same sequence, they are allowed to be blocked by, or pass, each other. d5b split read completions with the same sequence id must remain in address order. d6 split read completions are allowed to be blocked by, or pass, split write completions. e2 split write completions are allowed to be blocked by, or pass, memory write transactions moving in the opposite direction (they have no ordering relationship). e3, e4 split write completions must be allowed to pass all split requests to avoid deadlock. e5, e6 split write completions are allowed to be blocked by, or pass, split read and write completions.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-1 12?error handling 12 error handling this section provides detailed information regarding pci 6520 error management. it also describes error status reporting and error operation disabling. 12.1 overview the pci 6520 checks, forwards, and generates parity on the primary and secondary interfaces. to maintain transparency, the pci 6520 can either forward the existing parity condition from one bus to the other, along with address and data, or regenerate the data parity on the other bus. to support error reporting on the pci bus, the pci 6520 implements the following: p_perr#, p_serr#, s_perr#, and s_serr# signals primary and secondary status registers (pcisr; pci:06h and pcissr; pci:1eh, respectively) device-specific p_serr# event disable and status registers (pserred; pci:64h and pserrsr; pci:6ah, respectively) 12.2 address parity errors the pci 6520 checks address parity for all bus transactions, and address and bus commands. when the pci 6520 detects an address parity error on the primary interface, the following occurs: 1. conventional pci mode ?if the command register parity error response enable bit is set (pcicr[6]=1; pci:04h), the pci 6520 does not claim the transaction with p_devsel#. if the parity error response enable bit is not set, the pci 6520 proceeds as usual and accepts the transaction if the transaction is directed to, or across, the pci 6520. pci-x mode ?with a pci-x split completion command, the pci 6520 receives the cycle as if there is no parity error. with a pci-x command other than split completion, the pci 6520 claims the bus as usual and immediately terminates the cycle with a target abort. in either case, the pci 6520 does not accept the cycle in its fifo operation. 2. pci 6520 sets the status register parity error detected bit (pcisr[15]=1; pci:06h). 3. pci 6520 asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b; pci:04h). when the pci 6520 detects an address parity error on the secondary interface, the following occurs: 1. conventional pci mode ?if the bridge control register parity error response enable bit is set (bcntrl[0]=1; pci:3eh), the pci 6520 does not claim the transaction with s_devsel#. if the parity error response enable bit is not set, the pci 6520 proceeds as usual and accepts the transaction if the transaction is directed to, or across, the pci 6520. pci-x mode ?with a pci-x split completion command, the pci 6520 receives the cycle as if there is no parity error. with a pci-x command other than split completion, the pci 6520 claims the bus as usual and immediately terminates the cycle with a target abort. in either case, the pci 6520 does not accept the cycle in its fifo operation. 2. pci 6520 sets the secondary status register parity error detected bit (pcissr[15]=1; pci:1eh), regardless of the parity error response enable bit state (pcicr[6]=x). 3. pci 6520 asserts s_serr# and sets the status register signaled system error bit (pcissr[14]=1). 12.3 attribute parity errors? pci-x mode pci-x attribute parity errors are managed in the same way as address parity errors. (refer to section 12.2.) 12.4 data parity errors when forwarding transactions, the pci 6520 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to manage the error condition.
section 12 error handling data parity errors pci 6520cb data book, version 2.0 12-2 preliminary ? 2004 plx technology, inc. all rights reserved. the following subsections describe, for each transaction, the sequence that occurs when a parity error is detected and the way in which the parity condition is forwarded across the bridge. 12.4.1 configuration write transactions to configuration space when the pci 6520 detects a data parity error during a type 0 configuration write transaction to configuration space, the following occurs: 1. if the command register parity error response enable bit is set (pcicr[6]=1; pci:04h), the pci 6520 asserts p_perr#. if the parity error response enable bit is not set, the pci 6520 does not assert p_perr#. in either case, the configuration register is written. 2. pci 6520 sets the status register parity error detected bit (pcisr[15]=1; pci:06h), regardless of the parity error response enable bit state (pcicr[6]=x). 12.4.2 read transactions when the pci 6520 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts p_perr# or s_perr#. for downstream transactions, when the pci 6520 detects a read data parity error on the secondary bus, the pci 6520: 1. asserts s_perr# two cycles following the data transfer, if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1; pci:3eh). 2. sets the secondary status register parity error detected bit (pcissr[15]=1; pci:1eh), regardless of the parity error response enable bit state (pcicr[6]=x). 3. sets the secondary status register data parity error detected bit (pcissr[8]=1), if bcntrl[0]=1. 4. returns the bad parity with the data to the initiator on the primary bus. if the data with the bad parity is prefetched and not read by the initiator on the primary bus, the data is discarded and data with bad parity is not returned to the initiator. 5. completes the transaction as usual. for upstream transactions, when the pci 6520 detects a read data parity error on the primary bus, the pci 6520: 1. asserts p_perr# two cycles following the data transfer, if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. sets the primary status register parity error detected bit (pcisr[15]=1). 3. sets the primary status register data parity error detected bit (pcisr[8]=1), if pcicr[6]=1. 4. returns the bad parity with the data to the initiator on the secondary bus. if the data with the bad parity is prefetched and not read by the initiator on the secondary bus, the data is discarded and data with bad parity is not returned to the initiator. 5. completes the transaction as usual. the pci 6520 returns to the initiator the data and parity received from the target. when the initiator detects a parity error on this read data and is enabled to report the error, the initiator asserts its perr# signal (which is then connected to the pci 6520 p_perr# or s_perr# signal, depending on the initiator bus) two cycles after the data transfer. it is assumed that the initiator is responsible for handling parity error conditions; therefore, when the pci 6520 detects the initiator?s perr# assertion while returning read data to the initiator, the pci 6520 takes no further action and completes the transaction as usual. 12.4.3 posted write transactions during downstream posted write transactions, when the pci 6520 is responding as a target and detects a data parity error on the initiator (primary) bus, it: 1. asserts p_perr# two cycles after the data transfer, if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. sets the primary interface status register parity error detected bit (pcisr[15]=1). 3. captures and forwards the bad parity condition to the secondary bus. 4. completes the transaction as usual.
section 12 data parity errors error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-3 12?error handling similarly, during upstream posted write transactions, when the pci 6520 is responding as a target and detects a data parity error on the initiator (secondary) bus, it: 1. asserts s_perr# two cycles after the data transfer, if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1). 2. sets the secondary interface status register parity error detected bit (pcissr[15]=1). 3. captures and forwards the bad parity condition to the primary bus. 4. completes the transaction as usual. during downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target?s assertion of s_perr#, the pci 6520: 1. sets the secondary status register data parity error detected bit (pcissr[8]=1), if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1). 2. asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the following conditions are met: primary interface command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b, respectively), and device-specific p_serr# disable bit for posted write parity errors is not set (pserred[1]=0; pci:64h), and secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1), and pci 6520 did not detect the parity error on the initiator (primary) bus ( that is , the parity error was not forwarded from the primary bus) during upstream write transactions, when a data parity error is reported on the target (primary) bus by the target?s assertion of p_perr#, the pci 6520: 1. sets the status register data parity error detected bit (pcisr[8]=1), if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the following conditions are met: primary interface command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b, respectively), and secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1), and pci 6520 did not detect the parity error on the initiator (secondary) bus ( that is , the parity error was not forwarded from the secondary bus) p_serr# assertion signals the parity error condition when the initiator is not sent information about an error having occurred. because the data is delivered with no errors, there is no other way to signal this information to the initiator. if a parity error is forwarded from the initiator bus to the target bus, p_serr# is not asserted. 12.4.4 delayed write transactions when the pci 6520 detects a data parity error during a delayed write transaction, it conditionally asserts perr#. the pci 6520 either passes or regenerates data parity to the target bus. a parity error can occur: during the original delayed write request transaction when the initiator repeats the delayed write request transaction when the pci 6520 completes the delayed write transaction to the target 12.4.4.1 conventional pci mode in conventional pci mode, when a delayed write transaction is queued, the address, command, address and data parity, data, and byte enable bits are captured and a target retry is returned to the initiator. when the pci 6520 detects a parity error on the write data for the initial delayed write request transaction, the following occurs: 1. if the parity error response enable bit corresponding to the initiator bus is set (primary? pcicr[6]=1, secondary?bcntrl[0]=1), the pci 6520 asserts p_perr# or s_perr# two
section 12 error handling data parity error reporting summary pci 6520cb data book, version 2.0 12-4 preliminary ? 2004 plx technology, inc. all rights reserved. clocks after the data. the pci 6520 always accepts the cycle, and can optionally pass the incorrect parity to the other bus, or regenerate the parity bit on the other bus (mscopt[3]=1; pci:46h). 2. pci 6520 sets the status register parity error detected bit corresponding to the initiator bus (primary?pcisr[15]=1, secondary? pcissr[15]=1), regardless of the parity error response enable bit state (pcicr[6]=x). following the initiating transaction (the first pci 6520 retry), the subsequent data parity error of a similar transaction on the initiating bus is detected as usual; however, the data parity error no longer affects fifo operation. the cycles are considered similar if they have the same address, command, byte enables and write data. the parity bit is not part of this ?similar? detection operation. therefore, if a data parity error occurs only in the parity bit (same data as before), the cycle operates as usual. conversely, if a data parity error occurs in the data segment (different data from the initiating write data), the pci 6520 treats the error as a new delayed write transaction. 12.4.4.2 pci-x mode in pci-x mode, a delayed write transaction is queued with its address, command, parity, data, and byte enable bits, then returns a split response to the initiator. when the pci 6520 detects a parity error on the write data, the following occurs: 1. if the parity error response enable bit corresponding to the initiator bus is set (primary? pcicr[6]=1, secondary?bcntrl[0]=1), the pci 6520 asserts p_perr# or s_perr#. the pci 6520 always accepts the cycle, and can optionally pass the incorrect parity to the other bus, or regenerate the parity bit on the other bus (mscopt[3]=1; pci:46h). 2. pci 6520 sets the status register parity error detected bit corresponding to the initiator bus (primary?pcisr[15]=1, secondary? pcissr[15]=1), regardless of the parity error response enable bit state (pcicr[6]=x). 12.4.5 split completion?pci-x mode when detecting a data parity error on the originating bus for a split completion other than a split completion message, the pci 6520 asserts p_perr# or s_perr# and sets the appropriate error status bit for that interface. the pci 6520 ?drives bad parity? when it forwards the split completion. when the pci 6520 detects a data parity error on the originating bus for a split completion message, the following occurs: pci-x-to-pci mode ?parity error is not considered in the fifo operation. if the split completion error bit is set to 1 (ad30=1), the pci 6520 signals a target abort; otherwise, it is considered to be a normal completion. pci-x-to-pci-x mode ?pci 6520 forwards the exact message with the incorrect parity bit to the other bus. 12.5 data parity error reporting summary in the previous subsections, the pci 6520 responses to data parity errors are presented according to transaction type in progress. this subsection organizes the pci 6520 responses to data parity errors according to the status bits set by the pci 6520 and the signals asserted. table 12-1 delineates the primary interface status register parity error detected bit status. this bit is set when the pci 6520 detects a parity error on the primary interface. table 12-2 delineates the secondary interface status register parity error detected bit status. this bit is set when the pci 6520 detects a parity error on the secondary interface. table 12-3 delineates the primary interface status register data parity error detected bit status. this bit is set under the following conditions: pci 6520 must be a master on the primary bus, and primary interface command register parity error response enable bit must be set (pcicr[6]=1)
section 12 data parity error reporting summary error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-5 12?error handling table 12-4 delineates the secondary interface status register data parity error detected bit status. this bit is set under the following conditions: pci 6520 must be a master on the secondary bus, and secondary interface bridge control register parity error response enable bit must be set (bcntrl[0]=1) table 12-5 delineates p_perr# assertion. this signal is set under the following conditions: pci 6520 is either the target of a write transaction or the initiator of a read transaction on the primary bus, and primary interface command register parity error response enable bit must be set (pcicr[6]=1), and pci 6520 detects a data parity error on the primary bus, or detects s_perr# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus table 12-6 delineates s_perr# assertion. this signal is set under the following conditions: pci 6520 is either the target of a write transaction or the initiator of a read transaction on the secondary bus, and secondary interface bridge control register parity error response enable bit must be set (bcntrl[0]=1), and pci 6520 detects a data parity error on the secondary bus, or detects p_perr# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus table 12-7 delineates p_serr# or s_serr# assertion. this signal is set under the following conditions: command register p_serr# enable and parity error response enable bits must be set (pcicr[8, 6]=11b, respectively), bridge control register parity error response enable bit must be set (bcntrl[0]=1)
section 12 error handling data parity error reporting summary pci 6520cb data book, version 2.0 12-6 preliminary ? 2004 plx technology, inc. all rights reserved. note: x = don?t care. table 12-1. primary interface pa rity error detected bit status primary parity error detected bit (pcisr[15]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 0 secondary x x 1 upstream primary x x 0 secondary x x 1 posted write downstream primary x x 0 secondary x x 0 upstream primary x x 0 secondary x x 1 delayed write downstream primary x x 0 secondary x x 0 upstream primary x x 0 secondary x x
section 12 data parity error reporting summary error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-7 12?error handling note: x = don?t care. table 12-2. secondary interface parity error detected bit status secondary parity error detected bit (pcissr[15]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 1 secondary x x 0 upstream primary x x 0 secondary x x 0 posted write downstream primary x x 0 secondary x x 0 upstream primary x x 1 secondary x x 0 delayed write downstream primary x x 0 secondary x x 0 upstream primary x x 1 secondary x x
section 12 error handling data parity error reporting summary pci 6520cb data book, version 2.0 12-8 preliminary ? 2004 plx technology, inc. all rights reserved. note: x = don?t care. table 12-3. primary interface data parity error detected bit status primary data parity error detected bit (pcisr[8]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x 0 posted write downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x 0 delayed write downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x
section 12 data parity error reporting summary error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-9 12?error handling note: x = don?t care. table 12-4. secondary interface data parity error detected bit status secondary data parity error detected bit (pcissr[8]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x 0 posted write downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x 0 delayed write downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x
section 12 error handling data parity error reporting summary pci 6520cb data book, version 2.0 12-10 preliminary ? 2004 plx technology, inc. all rights reserved. notes: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. table 12-5. p_perr# assertion p_perr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 1 secondary x x 0 (asserted) upstream primary 1 x 1 secondary x x 0 posted write downstream primary 1 x 1 secondary x x 1 upstream primary x x 1 secondary x x 0 delayed write downstream primary 1 x 0* secondary 1 1 1 upstream primary x x 1 secondary x x
section 12 data parity error reporting summary error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-11 12?error handling note: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. table 12-6. s_perr# assertion s_perr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 0 (asserted) secondary x 1 1 upstream primary x x 1 secondary x x 1 posted write downstream primary x x 1 secondary x x 1 upstream primary x x 0 secondary x 1 1 delayed write downstream primary x x 1 secondary x x 0* upstream primary 1 1 0 secondary x 1
section 12 error handling data parity error reporting summary pci 6520cb data book, version 2.0 12-12 preliminary ? 2004 plx technology, inc. all rights reserved. notes: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. ** parity error detected on the target (primary) bus, but not on the initiator (secondary) bus. table 12-7. p _serr# or s_serr# for data parity error assertio n p_serr# or s_serr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 1 secondary x x 1 upstream primary x x 1 secondary x x 1 posted write downstream primary x x 0* (asserted) secondary 1 1 0** upstream primary 1 1 1 secondary x x 1 delayed write downstream primary x x 1 secondary x x 1 upstream primary x x 1 secondary x x
section 12 system error (p_serr#) reporting error handling pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 12-13 12?error handling 12.6 system error (p_serr#) reporting the pci 6520 uses the p_serr# signal to conditionally report a number of system error conditions in addition to the special case parity error conditions. in this data book, when p_serr# assertion is discussed, the following conditions are assumed: for the pci 6520 to assert p_serr#, the command register p_serr# enable bit must be set (pcicr[8]=1) when the pci 6520 asserts p_serr#, the pci 6520 must also set the status register signaled system error bit (pcisr[14]=1) in compliance with p-to-p bridge r1.2 , the pci 6520 asserts p_serr# when it detects s_serr# input asserted and the bridge control register s_serr# enable bit is set (bcntrl[1]=1). in addition, the pci 6520 also sets the secondary status register signaled system error bit (pcissr(14]=1). the pci 6520 also conditionally asserts p_serr# for the following conditions: master abort detected during posted write transaction (on the secondary bus) target abort detected during posted write transaction (on the secondary bus) posted write data discarded after 2 24 delivery attempts (2 24 target retries received) s_perr# reported on the target bus during a posted write transaction (refer to section 12.5) delayed write data discarded after 2 24 delivery attempts (2 24 target retries received) delayed read data cannot be transferred from the target after 2 24 attempts (2 24 target retries received) master timeout on delayed transaction the device-specific p_serr# status register reports the reason for p_serr# assertion. most of these events have additional device-specific disable bits in the p_serr# event disable register that can mask p_serr# assertion for specific events. the master timeout condition has s_serr# and p_serr# enable bits for that event in the bridge control register (bcntrl[12:11], respectively), and therefore does not have a device-specific disable bit.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 13-1 13?exclusive access 13 exclusive access this section describes p_lock# and s_lock# signal use to implement exclusive access to a target for transactions crossing the pci 6520, including concurrent locks, and acquiring and ending exclusive access. 13.1 concurrent locks the primary and secondary bus lock mechanisms concurrently operate, except when a locked transaction is crossing the pci 6520. a primary master can lock a primary target without affecting the lock status on the secondary bus, and vice versa. this means that a primary master can lock a primary target concurrent with a secondary master locking a secondary target. 13.2 acquiring exclusive access across pci 6520 for a pci bus, before acquiring access to the p_lock# and/or s_lock# signal and starting a series of locked transactions, the initiator must first verify whether the following conditions are met: pci bus is idle, and p_lock# and/or s_lock# is de-asserted the initiator leaves p_lock# and/or s_lock# de-asserted during the address phase and asserts p_lock# and/or s_lock# one clock cycle later. target lock is achieved after the target completes a data transfer. locked transactions can cross the pci 6520 in the downstream and upstream directions, from the primary-to-secondary bus and vice versa. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus, but also the lock on every bus between its bus and the target bus. when the pci 6520 detects an initial locked transaction on the primary bus that is intended for a target on the secondary bus, the pci 6520 samples the address, transaction type, byte enable, and parity bits, and the s_lock# signal. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. the first locked transaction must be a read transaction. subsequent locked transactions can be write or read transactions. posted memory write transactions that are part of the locked-transaction sequence are nevertheless posted. memory read transactions that are part of the locked-transaction sequence are not prefetched. when the locked delayed read request is queued, the pci 6520 does not queue further transactions until the locked sequence is complete. the pci 6520 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the opposite side of the pci 6520. the pci 6520 allows transactions queued before the locked transaction to complete before initiating the locked transaction. when the locked delayed read request moves to the head of the delayed transaction queue, the pci 6520 initiates the request as a locked read transaction by de-asserting s_lock# on the target bus during the first address phase, then re-asserting s_lock# one cycle later. if s_lock# was previously asserted (used by another initiator), the pci 6520 waits to request access to the secondary bus until s_lock# is sampled de-asserted when the target bus is idle. note that the existing lock on the target bus did not cross the pci 6520; otherwise, the pending queued locked transaction would not have queued. when the pci 6520 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. when the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, byte enable, and parity bits, the pci 6520 transfers the read data back to the initiator, and the lock is also established on the primary bus. for the pci 6520 to recognize and respond to the initiator, the initiator?s subsequent read transaction attempts must use the locked-transaction sequence (de-assert p_lock# during the address phase, then re-assert p_lock# one cycle later). if the p_lock# sequence is not used in subsequent attempts, a master timeout condition may result. when a master timeout condition occurs, p_serr# is conditionally
section 13 exclusive access ending exclusive access pci 6520cb data book, version 2.0 13-2 preliminary ? 2004 plx technology, inc. all rights reserved. asserted, the read data and queued read transaction are discarded, and s_lock# is de-asserted on the target bus. after the intended target is locked, subsequent locked transactions initiated on the initiator bus that are forwarded by the pci 6520 are driven as locked transactions on the target bus. when the pci 6520 receives a master or target abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on the initiator or target bus. the pci 6520 resumes unlocked transaction forwarding in both directions. 13.3 ending exclusive access after the lock is acquired on the initiator and target buses, the pci 6520 must maintain the lock on the target bus for subsequent locked transactions until the initiator relinquishes the lock. the only time a target retry causes the lock to be relinquished is on the first transaction of a locked sequence. on subsequent transactions in the sequence, the target retry has no effect on the p_lock# and/or s_lock# signal status. an established target lock is maintained until the initiator relinquishes the lock. the pci 6520 does not recognize whether the current transaction is the last in a sequence of locked transactions until the initiator de-asserts p_lock# and/or s_lock# at the end of the transaction. when the last locked transaction is a delayed transaction, the pci 6520 previously completed the transaction on the secondary bus. in this case, when the pci 6520 detects that the initiator has relinquished the p_lock# and/or s_lock# signal by sampling the signal de-asserted while p_frame# or s_frame# is de-asserted, the pci 6520 de-asserts p_lock# and/or s_lock# on the target bus when possible. because of this behavior, p_lock# and/or s_lock# may not be de-asserted until several cycles after the last locked transaction completes on the target bus. after de-asserting p_lock# and/or s_lock# to indicate the end of a sequence of locked transactions, the pci 6520 resumes unlocked transaction forwarding. when the last locked transaction is a posted write, the pci 6520 de-asserts p_lock# and/or s_lock# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. when the pci 6520 receives a master or target abort in response to a locked delayed transaction, the pci 6520 returns a master or target abort when the initiator repeats the locked transaction. the initiator must then de-assert p_lock# and/or s_lock# at the end of the transaction. the pci 6520 sets the appropriate status bits, flagging the abnormal target termination condition, and normal forwarding of unlocked posted and delayed transactions resumes. when the pci 6520 receives a master or target abort in response to a locked posted write transaction, the pci 6520 cannot communicate that status to the initiator. the pci 6520 asserts p_serr# on the initiator bus when a master or target abort is received during a locked posted write transaction, if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). p_serr# is asserted for the master abort condition if the bridge control register master abort mode bit is set (bcntrl[5]=1; pci:3eh). note: the pci 6520 has an option to ignore the lock protocol, by clearing the secondary and/or primary lock enable bits (mscopt[14:13]=00b; pci:46h, respectively).
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 14-1 14?pci bus arbitration 14 pci bus arbitration this section describes primary and secondary bus arbitration and bus parking. 14.1 overview the pci 6520 must arbitrate for use of the secondary bus when forwarding downstream transactions, and for the primary bus when forwarding upstream transactions. the primary bus arbiter is external to the pci 6520 (typically located on the motherboard). for the secondary pci bus, the pci 6520 has a built-in internal arbiter. the internal arbiter can be disabled, allowing use of an external arbiter for secondary bus arbitration. 14.2 primary pci bus arbitration the pci 6520 uses a request output pin and one grant input pin (p_req# and p_gnt#, respectively) for primary pci bus arbitration. the pci 6520 asserts p_req# when forwarding transactions upstream ( that is , when operating as an initiator on the primary pci bus). when there are one or more pending transactions in the upstream direction queues? posted write data or delayed transaction requests? the pci 6520 maintains p_req# assertion. however, if a target retry, disconnect, or abort is received in response to a pci 6520-initiated transaction on the primary pci bus, the pci 6520 de-asserts p_req# for two pci clock cycles. for all cycles passing through the bridge, p_req# is not asserted until the complete transaction request is queued. if the pci 6520 asserts p_req# and the primary bus external arbiter asserts p_gnt# to grant the bus to the pci 6520, the pci 6520 initiates a transaction on the primary bus on the next pci clock cycle. if the primary bus external arbiter asserts the pci 6520 p_gnt# signal when p_req# is not asserted, the pci 6520 parks p_ad x , p_cbe x #, p_par, and p_par64 by driving these signals to valid logic levels. if the primary bus is parked on the pci 6520 and the pci 6520 has a transaction to initiate on the primary bus, the pci 6520 initiates the transaction if p_gnt# remained asserted during the cycle prior to the start of the transfer. 14.3 secondary pci bus arbitration the pci 6520 implements a secondary pci bus internal arbiter, which supports up to eight external bus masters in addition to the pci 6520. if required, the internal arbiter can be disabled, allowing use of an external arbiter for secondary bus arbitration. 14.3.1 secondary bus arbitration using internal arbiter to use the internal arbiter, the secondary bus internal arbiter enable pin, s_cfn#, must be tied low. the pci 6520 has eight secondary bus request input and grant output pins (s_req[7:0]# and s_gnt[7:0]#, respectively) to support external secondary bus masters. if s_cfn# is high, s_req0# and s_gnt0# are re-configured as output and input, respectively, and s_gnt[7:1]# and s_req[7:1]# are driven high. the pci 6520 uses a two-level arbitration scheme, whereby arbitration is divided into two groups?low- and high-priority. the low-priority group represents a single entry in the high-priority group. therefore, if the high-priority group consists of n masters, the highest priority is assigned to the low-priority group at least once every n +1 transactions. priority changes evenly among the low-priority group. therefore, assuming all masters request the bus, members of the high-priority group are serviced n transactions out of n +1, while one member of the low-priority group is serviced once every n +1 transactions. each master can be assigned to a low- or high-priority group, through the arbiter control register (acntrl; pci:42h). each group can be programmed to use a rotating or fixed-priority scheme, through the internal arbiter control register group fixed arbitration bits (iacntrl[2, 0]; pci:50h).
section 14 pci bus arbitration secondary pci bus arbitration pci 6520cb data book, version 2.0 14-2 preliminary ? 2004 plx technology, inc. all rights reserved. 14.3.2 rotating-priority scheme the secondary arbiter supports a programmable two-level rotating algorithm that enables the eight request/grant pairs to control up to eight external bus masters. in addition, there is a request/grant pair internal to the pci 6520, which allows the device to request and be granted access to the secondary bus. figure 14-1 is an example of the internal arbiter wherein four masters, including the pci 6520, are in the high-priority group, and five masters are in the low-priority group. using this example, if all requests are always asserted, the highest priority rotates among the masters in the following way (the pci 6520 is denoted as b; high-priority members are provided in italic type, and low-priority members in boldface type): b, m0, m1, m2, m3 , b, m0, m1, m2, m4 , b, m0, m1, m2, m5 , and so forth if all masters are assigned to one group, the algorithm defaults to a rotating-priority among all masters. after reset, all external masters are assigned to the low-priority group, and the pci 6520 to the high-priority group. therefore, by default, the pci 6520 receives highest priority on the secondary bus every other transaction and priority rotates evenly among the other masters. figure 14-1. secondary bus arbiter example note: in figure 14-1, ?lpg? denotes ?low-priority group.? priorities are re-evaluated upon s_frame# assertion ( that is , at the start of each new transaction on the secondary pci bus). from this point, until the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request asserted. if a grant signal for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant signal corresponding to the new higher priority request on the next pci clock cycle. when priorities are re-evaluated, the highest priority is assigned to the next highest priority master, relative to the master that initiated the previous transaction. the master that initiated the last transaction now has the lowest priority within its group. priority is also re-evaluated if the requesting agent de-asserts its request without generating cycles while the request was granted. if the pci 6520 detects that an initiator has failed to assert s_frame# after 16 cycles of grant signal assertion and a secondary bus idle condition, the arbiter re-evaluates grant assignment. if another initiator asserts req# to request the bus, the pci 6520 switches the grant to the new initiator; otherwise, the same grant is asserted to the same initiator, even if the pci 6520 does not assert s_frame# within 16 cycles. 14.3.3 fixed-priority scheme the pci 6520 also supports a fixed-priority scheme within the low- and high-priority groups. in this case, the internal arbiter control register controls whether the low- or high-priority group uses the fixed or rotating-priority scheme (iacntrl[2, 0]; pci:50h). if using a fixed-priority scheme, a master within the group is assigned the highest priority within its group, and an option is set to control the priority of other masters relative to the highest priority master. this is controlled through the internal arbiter control register highest priority master and group arbitration order bits (iacntrl [11:4, 3, 1]; pci:50h). using the example provided in figure 14-1, but with the groups at fixed-priority, suppose that: master 7 (m7) has the highest priority of the low-priority group (iacntrl[7:4]=0111b) pci 6520 (b) has the highest priority of the high-priority group (iacntrl[11:8]=1000b) priority decreases in ascending order of masters for both groups (iacntrl[3, 1]=00b) m1 m2 lpg m0 b m3 m4 m5 m7 m6
section 14 arbitration bus parking pci bus arbitration pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 14-3 14?pci bus arbitration the order of priority with the highest first is as follows: b, m0, m1, m2, m7 , m3 , m4 , m5 , m6 if iacntrl[3, 1]=11b, priority increases with ascending order of bus master and the order becomes: b , m2 , m1 , m0 , m7 , m6 , m5 , m4 , m3 take care when using fixed arbitration in the low-priority group. as previously noted, the low-priority group receives the grant only when there are no high-priority group requests. when the arbiter switches to the low-priority group, the highest priority master requesting the bus within that group receives the grant. if there are several requests issued by the high-priority group members and the high-priority master in the low-priority group, then lower priority devices in the low-priority group may have to wait before receiving the grant. to prevent bus contention, if the secondary pci bus is idle, the arbiter waits at least one clock cycle between the s_gnt x # de-assertion and assertion of the next s_req x #. if the secondary pci bus is busy ( that is , s_frame# or s_irdy# is asserted) when another bus master requests the bus, the arbiter can de-assert one grant and assert the next grant during the same pci clock cycle. 14.3.4 secondary bus arbitration using external arbiter the internal arbiter can be disabled by pulling the secondary bus internal arbiter enable pin (s_cfn#) high. an external arbiter must be used if more than one bus master is required to initiate cycles on the secondary bus. when s_cfn# is tied high, the pci 6520 reconfigures two pins to be external request and grant pins. s_req0# is re-configured to be the external request output from the pci 6520 and is used by the pci 6520 to request the secondary bus. s_gnt0# is re-configured to be the pci 6520 external grant input from the external arbiter. if the pci 6520 requests the secondary pci bus (s_req0# asserted) and the external arbiter grants the bus to the pci 6520 (s_gnt0# asserted), the pci 6520 initiates a transaction on the secondary bus one clock cycle later. if the secondary bus external arbiter asserts s_gnt0# when s_req0# is not asserted, the pci 6520 parks s_ad x , s_cbe x #, s_par, and s_par64 by driving these signals to valid logic levels. when using an external arbiter, the unused secondary bus grant outputs (s_gnt[7:1]#) are driven high. unused secondary bus request inputs (s_req[7:1]#) must be pulled high. 14.4 arbitration bus parking bus parking refers to driving the ad x , cbe x #, par, and par64 lines to a known value while the bus is idle. the pci bus is parked on the pci 6520 primary or secondary bus when either or both buses are idle. bus parking occurs when the bus grant to the pci 6520 on the parked bus is being asserted, and the pci 6520 request for that bus is not asserted. the ad x and cbe x # signals are first driven low (0), then the par and par64 signals are driven low (0) one cycle later. when the gnt# signal for the parked bus is de-asserted, the pci 6520 places the ad x , cbe x #, par, and par64 signals into a high-impedance state on the next pci clock cycle. if the pci 6520 is parking and wants to initiate a transaction on that bus, the pci 6520 can start the transaction on the next pci clock cycle by asserting frame# if gnt# remains asserted. 14.4.1 software controlled pci 64-bit extension signals parking by reading the input status of dev64#, software can determine which pci 6520 port is interfaced to a backplane and whether it can perform 64-bit transactions. if only 32-bit transactions can be used, then software can program the pci 6520 to drive the unused 64-bit extension signals to 0. this is an optional mechanism for use in the event that external pull-up resistors are not desirable (which may be the case in high-speed applications) and prevents the 64-bit extension signals from floating. the control bits are secondary and primary 64-bit extension signals park , located in rrc[2:1]; pci:9ch, respectively.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 15-1 15?gpio interface 15 gpio interface this section describes the gpio interface pins, control registers, and serial stream. 15.1 gpio interface pins the pci 6520 provides eight, general-purpose i/o (gpio) interface pins. (refer to table 15-1.) during normal operation, the configuration registers control the gpio interface. during secondary reset, the gpio[2:0] and msk_in can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. the gpio[7:0] pins have weak internal pull-up resistors. external pull-up or pull-down resistors are recommended. 15.2 gpio control registers the gpio registers can be accessed from both sides of the bus. during normal operation, the gpio interface is controlled by the following three gpio configuration registers: output enable (gpiooe) output data (gpiood) input data (gpioid) the gpio[7:4] and gpio[3:0] configuration registers consist of five 8-bit fields: output enable write 1 to set (gpiooe x [7:4]) output enable write 1 to clear (gpiooe x [3:0]) output data write 1 to set (gpiood x [7:4]) output data write 1 to clear (gpiood x [3:0]) input data (gpioid x [7:4]) the output enable fields control whether the gpio signals are inputs or outputs. each signal is independently controlled by a bit in each output enable field. if 1 is written to the write 1 to set field, the corresponding pin is activated as an output. if 1 is written to the write 1 to clear field, the output driver is placed into a high-impedance state, and the pin is input only. writing zeros (0) to these registers has no effect. the reset state for these signals is input only. the output data fields also use the write 1 to set and clear methods. if 1 is written to the write 1 to set field and the pin is enabled as an output, the corresponding gpio output is driven high. if 1 is written to the write 1 to clear field and the pin is enabled as an output, the corresponding gpio output is driven low. writing zeros (0) to these registers has no effect. the value written to the output data register is driven only when the gpio signal is configured as output. a type 0 configuration write operation is used to program these registers. the reset value for the output is 0. the input data field is read-only and reflects the current value of the gpio[7:0] pins. a type 0 configuration read operation to the input data register returns the values of these pins. the gpio[7:0] pins can be read at any time, whether configured as input only or bi-directional. 15.3 gpio serial stream refer to section 4.2.2, ?secondary clock control,? on page 4-1. table 15-1. gpio pin alternate functions gpio pin alternate function gpio0?pull-up functions as secondary bus clock mask shift register clock output when p_rstin# is asserted. gpio1?pull-up no alternate function. gpio2 ?pull-up functions as shift/load control output to shift register when p_rstin# is asserted. gpio3 ?pull-up no alternate function. gpio4 ?pull-up gpio5 ?pull-up gpio6 ?pull-up gpio7 ?pull-up

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 16-1 16?supported commands 16 supported commands this section discusses the pci 6520 conventional pci and pci-x command set. 16.1 primary interface command set table 16-1 delineates the pci 6520 primary interface conventional pci and pci-x command set. table 16-1. primary interface supported commands p_cbe[3:0]# command support conventional pci pci-x 0000b interrupt acknowledge not supported. 0001b special cycle 0010b i/o read if the address is within pass-through i/o range, the transaction is claimed and passed through. if the address points to an i/o-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0011b i/o write same as i/o read (p_cbe[3:0]#=0010b). 0100b reserved ? 0101b 0110b memory read memory read dword if the address is within pass-through memo ry range, the transaction is claimed and passed through. if the address points to a memory-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0111b memory write same as memory read (p_cbe[3:0]#=0110b). 1000b reserved alias to memory read block conventional pci ? not supported. pci-x ?treated as a memory read block (p_cbe[3:0]#=1110b). 1001b reserved alias to memory write block conventional pci ? not supported. pci-x ?treated as a memory write block (p_cbe[3:0]#=1111b).
section 16 supported commands primary interface command set pci 6520cb data book, version 2.0 16-2 preliminary ? 2004 plx technology, inc. all rights reserved. 1010b configuration read type 0 configuration read, claimed if the p_idsel line is asserted; otherwise, the read is ignored. if claimed, the targ et internal register(s) is read. never passed through. type 1 configuration read, claimed if the p_idsel line is asserted; otherwise, the read is ignored. if the target bus is the bridge?s secondary bus, the transaction is claimed and passed thr ough as a type 0 configuration read. if the target bus is a subordinate bus t hat exists behind the bridge (but not equal to the secondary bus), the transacti on is claimed and passed through as a type 1 configuration read. 1011b configuration write type 0 configuration write, same as configuration read (p_cbe[3:0]#=1010b). type 1 configuration write (not special cycle request), same as configuration read (p_cbe[3:0]#=1010b). configuration write as special cycle request (device = 1fh, function = 7h). if the target bus is the bridge?s secondary bus, the transaction is claimed and passed through as a special cycle. if the target bus is a subordinate bus t hat exists behind the bridge (but not equal to the secondary bus), the trans action is claimed and passed through unchanged as a type 1 configuration write. 1100b memory read multiple split completion conventional pci ?treated as a memory read (p_cbe[3:0]#=0110b). pci-x ?split completion. 1101b dac lower 32 bits of the address are driven out on p_ad[31:0], followed by the upper 32 bits. 1110b memory read line memory read block conventional pci ?treated as a memory read (p_cbe[3:0]#=0110b). pci-x ?memory read block. 1111b memory write and invalidate memory write block conventional pci ?treated as a memory write (p_cbe[3:0]#=0111b). pci-x ?memory write block. table 16-1. primary interface supported commands (continued) p_cbe[3:0]# command support conventional pci pci-x
section 16 secondary interface command set supported commands pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 16-3 16?supported commands 16.2 secondary interface command set table 16-2 delineates the pci 6520 secondary interface conventional pci and pci-x command set. table 16-2. secondary interface supported commands s_cbe[3:0]# command support conventional pci pci-x 0000b interrupt acknowledge not supported. 0001b special cycle 0010b i/o read if the address is within pass-through i/ o range, the transaction is claimed and passed through. if the address points to an i/o-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0011b i/o write same as i/o read (s_cbe[3:0]#=0010b). 0100b reserved ? 0101b 0110b memory read memory read dword if the address is within pass-through memory range, the transaction is claimed and passed through. if the address points to a memory-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0111b memory write memory write same as memory read (s_cbe[3:0]#=0110b). 1000b reserved alias to memory read block conventional pci ? not supported. pci-x ?treated as a memory read block (s_cbe[3:0]#=1110b). 1001b reserved alias to memory write block conventional pci ? not supported. pci-x ?treated as a memory write block (s_cbe[3:0]#=1111b).
section 16 supported commands secondary interface command set pci 6520cb data book, version 2.0 16-4 preliminary ? 2004 plx technology, inc. all rights reserved. 1010b configuration read upstream configuration read cycles. not supported. 1011b configuration write type 0 configuration write. not supported. type 1 configuration write (not a special cycle request). not supported. configuration write as special cycle request (device = 1fh, function = 7h). if the target bus is the bridge?s prim ary bus, the transaction is claimed and passed through as a special cycle. if the target bus is neither the prim ary bus nor in the range of buses defined by the bridge?s secondary and subordinate bus registers, the transaction is claimed and passed through unchanged as a type 1 configuration write. if the target bus is not the bridge?s primary bus, but is within the range of buses defined by the bridge?s secondar y and subordinate bus registers, the transaction is ignored. 1100b memory read multiple split completion conventional pci ?treated as a memory read (s_cbe[3:0]#=0110b). pci-x ?split completion. 1101b dac lower 32 bits of the address are driven out on s_ad[31:0], followed by the upper 32 bits. 1110b memory read line memory read block conventional pci ?treated as a memory read (s_cbe[3:0]#=0110b). pci-x ?memory read block. 1111b memory write and invalidate memory write block conventional pci ?treated as a memory write (s_cbe[3:0]#=0111b). pci-x ?memory write block. table 16-2. secondary interface supported commands (continued) s_cbe[3:0]# command support conventional pci pci-x
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 17-1 17?bridge behavior 17 bridge behavior this section presents various bridge behavior scenarios that occur when the target responds to a cycle generated by the pci 6520, on behalf of the initiating master. 17.1 bridge actions for various cycle types a pci cycle is initiated by frame# assertion. in a bridge, there are several possibilities for this to occur. table 17-1 summarizes these possibilities, and delineates the pci 6520 action for various cycle types. after the pci cycle is initiated, a target then has up to four cycles to respond before a master abort is initiated. if the target detects an address hit, it asserts devsel# in the cycle corresponding to the configuration status register devsel# timing bits (pcisr[10:9]; pci:06h or pcissr[10:9]; pci:1eh). pci cycle termination can occur in a number of ways. normal termination begins by the initiator (master) de-asserting frame#, with irdy# being asserted (or remaining asserted) on the same cycle. the cycle completes when trdy# and irdy# are simultaneously asserted. the target should de-assert trdy# for one cycle following final assertion (sustained three-state signal). table 17-1. bridge actions for various cycle types initiator target pci 6520 response master on primary port target on the same primary port does not respond. this situation is detected by decoding the address and monitoring p_devsel# for other fast and medium-speed devices on the primary port. target on secondary port asserts p_devsel# and normally terminates the cycle if posted; otherwise, returns with a retry. next, passes the cycle to the appropriate port. when the cycle completes on the target port, the pci 6520 waits for the initiator to repeat the same cycle and end with normal termination. target not on primary nor secondary port does not respond and the cycle terminates as a master abort. master on secondary port target on the same secondary port does not respond. target on primary or other secondary port asserts s_devsel# and normally terminates the cycle if posted; otherwise, returns with a retry. next, passes the cycle to the appropriate port. when the cycle completes on the target port, the pci 6520 waits for the initiator to repeat the same cycle and end with normal termination. target not on primary nor other secondary port does not respond.
section 17 bridge behavior abnormal termination (m aster abort, initiated by bridge master) pci 6520cb data book, version 2.0 17-2 preliminary ? 2004 plx technology, inc. all rights reserved. 17.2 abnormal termination (master abort, initiated by bridge master) a master abort indicates that the pci 6520, operating as a master, receives no response from a target ( that is , no target asserts p_devsel# or s_devsel#). the bridge de-asserts frame#, then de-asserts irdy#. 17.3 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par and s_par signals. parity should be even [ that is , an even number of ones (1)] across ad[63:0], cbe[7:0]#, par, and par64. parity information on par is valid the cycle after ad[63:0] and cbe[7:0]#, are valid. for all address phases, if a parity error is detected, the error is reported on the p_serr# signal by asserting p_serr# for one cycle, then placing two cycles into a high-impedance state after the bad address. p_serr# can be asserted only if the command register p_serr# and parity error response bits are both set to 1 (pcicr[8, 6]=11b; pci:04h, respectively). for write data phases, a parity error is reported by asserting p_perr# two cycles after the data phase and remains asserted for one cycle when pcicr[8]=1. the target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. address parity error detection causes the pci bridge target to not claim the bus (p_devsel# remains inactive). the cycle then terminates with a master abort. when the bridge is operating as master, a data parity error during a read cycle results in the bridge master initiating a master abort.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 18-1 18?pci flow-through optimization 18 pci flow-through optimization this section describes flow-through optimization, including precautions when using non-optimized pci master devices, posted write and delayed read flow through, read cycle optimization, and read prefetch boundaries. 18.1 overview the pci 6520 operates in flow-through mode when data from the same transaction is simultaneously transferred on both sides of the bridge ( that is , data on one side of the bridge ?flows through? to the other side of the bridge). the pci 6520 has several options to optimize pci transfers after flow-though mode is achieved. flow-through mode improves pci bus utilization and efficiency. if data transfers on one side of the bridge are broken into several transactions on the other side of the bridge, poor bus efficiency results. by using flow-through mode, the pci 6520 improves bus efficiency for posted writes, delayed reads, and reads to prefetchable space. 18.2 precautions when using non-optimized pci master devices the pci 6520 is capable of high-performance prefetching. however, some pci masters may be unable to prefetch large amounts of data. this may be due to a small internal buffer size or other limiting factors. for example , if data is being read from a register or fifo-based architecture, valuable data may be lost if the host prematurely terminates a prefetch cycle (ideally such spaces would not be listed as prefetchable). under these circumstances, the default prefetch values may be overly aggressive and affect overall performance. in this case, tune default prefetching by reprogramming the prefetch registers, as listed in table 18-1. (refer to section 6, ?registers,? for a detailed description of these registers.) the serial eeprom can also be used to program the configuration space upon reset. 18.3 posted write flow through during flow through of posted write cycles, if there is only one data transfer pending in the internal post memory write queue, the pci 6520 de-asserts irdy# on the target side and waits seven clocks for additional data from the initiator before terminating the cycle. if new write data is received from the initiator during this period, the pci 6520 re-asserts irdy# and continues with the write cycle. if new write data is not received during this period, the pci 6520 terminates the cycle to the target with the last data from the queue and later finishes the cycle. the flow-through control registers for posted writes are detailed in section 6, ?registers.? (refer to pftcr[2:0]; pci:44h and sftcr[2:0]; pci:4eh.) table 18-1. reprogramming prefetch registers configuration space register data value primary initial prefetch count (pitlpcnt; pci:48h) same value as cache line size register (pciclsr; pci:0ch). most pcs set this value to 08h. secondary initial prefetch count (sitlpcnt; pci:49h) primary incremental prefetch count (pincpcnt; pci:4ah) 0h secondary incremental prefetch count (sincpcnt; pci:4bh) primary maximum prefetch count (pmaxpcnt; pci:4ch) secondary maximum prefetch count (smaxpcnt; pci:4dh)
section 18 pci flow-through optimization delayed read flow through pci 6520cb data book, version 2.0 18-2 preliminary ? 2004 plx technology, inc. all rights reserved. 18.4 delayed read flow through for flow through of delayed read cycles, if the internal read queue is almost full, the pci 6520 de-asserts irdy# on the target side and waits seven clocks for additional data from the initiator before terminating the cycle. if additional space becomes available in the internal read queue before the irdy# inactive period ends, the pci 6520 re-asserts irdy# and proceeds with the next read data phase. if no additional space becomes available in the internal read queue, the current data phase becomes the last (irdy# is asserted) and the cycle disconnects at the end of the data phase. the flow-through control registers for delayed reads are detailed in section 6, ?registers.? (refer to pftcr[6:4]; pci:44h and sftcr[6:4]; pci:4eh.) 18.5 read cycle optimization read cycle optimization increases the probability of flow through occurring during read accesses to prefetchable memory regions. to improve the probability of flow through, the amount of data to be prefetched must be correctly configured. if the pci 6520 prefetches insufficient data, flow through does not occur because prefetching on the target side completes before the initiator retries the read access. under these circumstances, the read cycles are divided into multiple cycles. if the pci 6520 prefetches excessive data and the internal fifos fill, the pci 6520 must wait for the initiator to retry the previous read cycle and then flush the unclaimed data before queuing subsequent cycles. the initial count is normally equivalent to the cache line size. this assumes that a master usually requires at least one cache line of data. the incremental count is used only when the pci 6520 does not detect flow through for the current cycle being prefetched during the initial prefetch count. the pci 6520 continues prefetching in increments until it reaches the maximum prefetch count, then disconnects the cycle. for read prefetching, the pci 6520 implements several registers that control the amount of data prefetched on the primary and secondary pci buses. the prefetch registers listed in table 18-1 can be used to optimize pci 6520 performance during read cycles. the pci 6520 prefetches until flow through occurs or prefetching must stop, based on the following conditions. prefetch continues while: (ipmc + ipc + ipc + ? + ipc) < mpc where: ipmc = initial prefetch maximum count ipc = incremental prefetch count, < ? mpc mpc = maximum prefetch count if the prefetch count did not reach mpc and flow through was achieved, the pci 6520 continues prefetching until the requesting master terminates the prefetch request. otherwise, when mpc is reached, the pci 6520 stops prefetching data. incremental prefetch can be disabled by setting ipc mpc. 18.5.1 primary and secondary initial prefetch count assuming that there is sufficient space in the internal fifo, the primary and secondary initial prefetch count registers (pitlpcnt; pci:48h and sitlpcnt; pci:49h, respectively) control the amount of data initially prefetched by the pci 6520 on the primary or secondary bus during reads to the prefetchable memory region. if flow through is achieved during this initial prefetch, the pci 6520 continues prefetching beyond this count.
section 18 read prefetch boundaries pci flow-through optimization pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 18-3 18?pci flow-through optimization 18.5.2 primary and secondary incremental prefetch count the primary and secondary incremental prefetch count registers (pincpcnt; pci:4ah and sincpcnt; pci:4bh, respectively) control the amount of prefetching that occurs after the initial prefetch. if flow through is not achieved during the initial prefetch, the pci 6520 attempts to prefetch additional data, until the fifo fills, or until the maximum prefetch count is reached. each subsequent prefetch is equal to the incremental prefetch count. 18.5.3 primary and secondary maximum prefetch count the primary and secondary maximum prefetch count registers (pmaxpcnt; pci:4ch and smaxpcnt; pci:4dh, respectively) limit the amount of prefetched data for a single entry available in the internal fifo at any time. during read prefetch cycles, the pci 6520 disconnects the cycle if the data count in the fifo for the current cycle reaches this value, and flow through has not been achieved. 18.6 read prefetch boundaries for memory read and memory read line commands, the pci 6520 prefetches from the starting address up to an address with an offset that is a multiple of the initial prefetch count. for example , if the starting address is 10h and the initial prefetch count is 20h, the pci 6520 prefetches only a 10h (20h to 10h) count. after this, the pci 6520 begins incremental prefetch until the maximum prefetch count is reached, or flow through is achieved. the exception to this is in the case of a 64-bit request and six or fewer dwords from the boundary, or a 32-bit request and four or fewer dwords from the boundary, in which the pci 6520 does not activate incremental prefetch. for memory read multiple commands, if the starting address is not 0, the pci 6520 first prefetches from the starting address up to the address with an offset equal to that of the initial prefetch count. after this, the pci 6520 prefetches one additional initial prefetch count. for example , if the starting address is 10h and the initial prefetch count is 20h, the pci 6520 first prefetches a 10h (20h to 10h) count, then continues to prefetch another 20h count. subsequent to this, incremental prefetch is invoked until the maximum prefetch count is reached or flow through is achieved.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 19-1 19?fifo architecture 19 fifo architecture this section describes fifo architecture, including how the fifos function with memory write and read commands, and how to split the read fifo into four 1-kb blocks. 19.1 overview the pci 6520 contains a 1-kb write fifo and 4-kb read fifo in both the downstream and upstream directions, for a total of 10 kb of data fifo. the fifo architecture is designed for optimal pci-x-to-pci and pci-x-to-pci-x bridging, with the following features: flow-through capable programmable prefetch byte counts of up to 2 kb on the pci-x port controllable number of outstanding adqs on the pci-x port figure 19-1. pci 6520 fifo architecture read data entry command delivery write data delivery four write entries 1-kb memory write buffer 4-dword i/o write buffer command entry four write entries 1-kb memory write buffer 4-dword i/o write buffer write data entry read data del i very write data delivery read data entry command del i very command ent ry write data entry read data del ivery four entries command queue four read entries 4-kb memory / i/o read buffer timeout flush or command end flush segmentable to four 1-kb fifo for each entry four entries command queue four read entries 4-kb memory / i / o read buffer timeout flush or command end flush segmentable to four 1-kb fifo for each entry primary port secondary port
section 19 fifo architecture memory writes pci 6520cb data book, version 2.0 19-2 preliminary ? 2004 plx technology, inc. all rights reserved. 19.2 memory writes this subsection describes pci-to-pci-x, pci-x-to- pci, and pci-x-to-pci-x memory writes. 19.2.1 pci-to-pci-x memory writes if the initiator writes more than 64 bytes, the pci 6520 absorbs the greatest amount of data possible into the write fifo. when the pci-x port becomes available and there are 64 or more bytes available in the fifo, the pci 6520 begins data delivery from the fifo to the pci-x port, using the byte count present in the fifo. if the initiator byte count is less than 64 bytes, the pci 6520 first receives all the bytes into the fifo, then delivers the bytes to the pci-x port. 19.2.2 pci-x-to-pci memory writes when functioning as a target and receiving data into the write fifo, the pci 6520 begins data delivery from the fifo when the opposite port is available. the pci-x byte count does not influence the start of data delivery to the pci port. 19.2.3 pci-x-to-pci-x memory writes when the pci 6520 is a target, it always accepts the greatest amount of data possible into the write fifo. concurrent with this process, when the opposite port is available and the incoming data reaches an adb boundary, the pci 6520 begins data delivery from the fifo. if the initiator byte count is less than 128 bytes and has not reached an adb boundary, the pci 6520 first receives, then delivers, all the bytes. 19.3 memory reads this subsection describes pci-to-pci-x, pci-x-to- pci, and pci-x-to-pci-x memory reads. 19.3.1 pci-to-pci-x memory reads when the pci 6520 receives a pci read command, the pci 6520 issues a read command to the pci-x port, using the programmed prefetch count specified by the following registers: primary initial prefetch count (pitlpcnt[2:1]; pci:48h) primary incremental prefetch count (pincpcnt; pci:4ah) secondary initial prefetch count (sitlpcnt[2:1]; pci:49h) secondary incremental prefetch count (sincpcnt; pci:4bh) regardless of the programmed prefetch count, the pci 6520 does not prefetch beyond 16 cache lines. if the count is equal to, or greater than, the maximum programmed outstanding adqs limit (default is 32) in the pci-x downstream and upstream split transaction registers (pcixdnstr; pci:fch and pcixupstr; pci:f8h, respectively), at least one pci-x read command is issued. in general, set the maximum programmed outstanding adqs to a value higher than the prefetch count so that the pci 6520 can issue multiple pci-x read requests. when data becomes available in the fifo, the pci 6520 begins data delivery to the pci port. prefetched data in the pci 6520 read fifo can either be flushed (if the pci initiator finishes its current read transaction) or preserved for a programmed time period. upon timeout, if the pci master has not returned to acquire additional data, the fifo flushes the remaining data. this feature can greatly enhance the pci-x bus bandwidth, as the pci 6520 can prefetch up to 16 cache lines of anticipated data for the pci devices.
section 19 memory reads fifo architecture pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 19-3 19?fifo architecture 19.3.1.1 prefetched da ta timeout flushing prefetched data timeout flushing can be controlled by way of the register bits listed in table 19-1. table 19-1. prefetched data timeout flushing control description bufcr[1]; pci:4fh buffer control smart prefetch enable. amount of data prefetched is defined in the maximum prefetch count registers (pmaxpcnt; pci:4ch and smaxpcnt; pci:4dh). defaults to 0. values after a prefetch command: 0 = remaining prefetched data is discarded upon completion of the current read command. 1 = remaining prefetched data is not discarded, but remains available for the next read command with consecutive address. the prefetched data is onl y discarded upon a timeout. the timeout period can be programmed using the smart prefetch timeout bits (bufcr[6:5]; pci:4fh). bcntrl[8]; pci:3eh bridge control primary master timeout. sets the maximum number of pci clocks for an initiator on the primary bus to repeat the de layed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks reset to 0. bcntrl[9]; pci:3eh bridge control secondary master timeout. sets the maximum number of pci clocks for an initiator on the secondary bus to repeat the delayed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks reset to 0.
section 19 fifo architecture memory reads pci 6520cb data book, version 2.0 19-4 preliminary ? 2004 plx technology, inc. all rights reserved. 19.3.1.2 setting the prefetch count 19.3.1.2.1 pci read from conventional pci port for details on pci read from pci port, refer to section 18, ?pci flow-through optimization.? 19.3.1.2.2 pci read from pci-x port for pci master reads from pci-x devices, the pci 6520 can be set up to prefetch data from the pci-x port to enhance system performance by minimizing pci access to the pci-x bus. when the pci 6520 receives a pci read command, the pci 6520 issues a read command to the pci-x port, using the programmed prefetch count specified by the following registers: primary initial prefetch count (pitlpcnt[2:1]; pci:48h) primary incremental prefetch count (pincpcnt; pci:4ah) secondary initial prefetch count (sitlpcnt[2:1]; pci:49h) secondary incremental prefetch count (sincpcnt; pci:4bh) 19.3.2 pci-x-to-pci memory reads after receiving the pci-x memory read command, the pci 6520 issues a pci memory read command to the pci port when the port becomes available. when sufficient data is received to read an adb boundary, the pci 6520 begins forwarding the read data to the pci-x port. if there is a mid-transaction wait period during which the pci port is not supplying the pci 6520 with sufficient data to reach the next adb boundary, the pci-x split completion cycle is disconnected so that the pci 6520 can serve another pci-x master. 19.3.3 pci-x-to-pci-x memory reads depending on the programmed outstanding adqs limit (default is 32) in the pci-x downstream and upstream split transaction registers (pcixdnstr; pci:fch and pcixupstr; pci:f8h, respectively)? the pci 6520 issues a read command to the opposite port until the requested and pending read byte counts have reached the maximum programmed outstanding adqs limit.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 20-1 20?power management 20 power management this section describes the power management feature. 20.1 overview the pci 6520 incorporates functionality that meets the requirements of pci power mgmt. r1.1 . these features include: pci power management registers, using the enhanced capabilities port (ecp) address mechanism support for d 0 , d 3hot , and d 3cold power management states support for d 0 , d 1 , d 2 , d 3hot , and d 3cold power management states for devices behind the bridge support for b 2 secondary bus power state when in the d 3hot power management state 20.2 power management transitions table 20-1 delineates the states and related actions the pci 6520 performs during power management transitions. (no other transactions are allowed.) table 20-1. states and related actions during power management transitions current state next state action d 0 d 1 during an unimplemented power state, the pci 6520 ignores the write to the power state bits (power state remains at d 0 , pmcsr[1:0]=00b; pci:e0h). d 2 d 3hot if enabled by the bpcc_en pin, the pci 6520 disables the secondary clocks and drives them low. d 3cold power removed from the pci 6520. a power-up reset must be performed to bring the pci 6520 to d 0 . d 3hot d 0 the pci 6520 enables secondary clock outputs and performs an internal chip reset. s_rstout# is not asserted. all registers are returned to the reset values and buffers are cleared. d 3cold power removed from the pci 6520. a power-up reset must be performed to bring the pci 6520 to d 0 . d 3cold d 0 during a power-up reset, the pci 6520 performs the standard power-up reset functions.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 21-1 21?vpd 21 vpd this section describes the vpd feature. the pci 6520 contains the vital product data (vpd) registers, as specified in pci r2.3 . vpd information is stored in the serial eeprom device, along with autoload information. the pci 6520 provides storage of 192 bytes of vpd data in the serial eeprom device. the vpd register block is located at offsets e8h to ech in pci configuration space. (refer to section 6.1.2.20, ?vpd capability.?) vpd also uses the enhanced capabilities port address mechanism.

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 22-1 22?testability/debug 22 testability/debug this section describes the jtag interface for use in testing and debugging the pci 6520. 22.1 jtag interface the pci 6520 provides a jtag boundary scan interface, which can be utilized to debug a pin?s board connectivity. 22.1.1 ieee 1149.1 test access port the ieee 1149.1 test access port (tap), commonly called the jtag (joint test action group) debug port, is an architectural standard described in ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture. the standard describes a method for accessing internal chip facilities using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. the enhancements, which comply with ieee standard 1149.1-1990 specifications for vendor-specific extensions, are compatible with standard jtag hardware for boundary-scan system testing. jtag signals ?jtag debug port implements the four required jtag signals?tck, tdi, tdo, tms?and the optional trst# signal. (refer to table 3-8, ?jtag/boundary scan pins,? on page 3-19 for signal descriptions.) jtag clock requirements ?tck signal frequency can range from dc to 10 mhz. jtag reset requirements ?jtag debug port logic and system simultaneously reset. the two methods for placing the pci 6520 jtag tap controller into the test-logic-reset state are as follows: upon receiving trst#, the jtag tap controller returns to the test-logic reset state hold the pci 6520 tms pin high while transitioning the pci 6520 tck pin five times 22.1.2 jtag instructions the jtag debug port provides the standard extest , sample/preload , clamp , highz , idcode , and bypass instructions. invalid instructions behave as bypass instructions. the pci 6520 returns the idcode values listed in table 22-1. table 22-2 lists the jtag instructions, along with their input codes. table 22-1. pci 6520 jtag idcode value m s b l s b 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 4-bit version 16-bit part number (pci 6520 when converted to decimal) 11-bit plx manufacturer identity 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 table 22-2. jtag instructions (ieee standard 1149.1-1990) instruction input code instruction input code extest 00000b highz 00101b sample/preload 00001b idcode 00110b clamp 00100b bypass 11111b
section 22 testability/debug jtag interface pci 6520cb data book, version 2.0 22-2 preliminary ? 2004 plx technology, inc. all rights reserved. 22.1.3 jtag boundary scan boundary scan description language (bsdl), ieee 1149.1b-1994, is a supplement to ieee standard 1149.1-1990 and ieee 1149.1a-1993, ieee standard test access port and boundary-scan architecture . bsdl, a subset of the ieee 1076-1993 standard vhsic hardware description language (vhdl), allows a rigorous description of testability features in components that comply with the standard. automated test pattern generation tools use bdsl for package interconnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical pin map, instruction set, and boundary register description. the logical port description assigns symbolic names to the pci 6520 pins. each pin has a logical type of in, out, in out, buffer, or linkage that defines the logical signal flow direction. the physical pin map correlates the pci 6520 logical ports to the physical pins of a specific package. a bsdl description can have several physical pin maps; each map is provided a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the pci 6520 in the various test modes defined by the standard. instruction set statements also support instruction descriptions unique to the pci 6520. the boundary register description lists each of its cells or shift stages. each cell has a unique number?the cell numbered 0 is the closest to the test data out (tdo) pin and the cell with the highest number is closest to the test data in (tdi) pin. each cell contains additional information, including: cell type logical port associated with the cell logical function of the cell safe value control cell number disable value result value 22.1.4 jtag reset input trst# the trst# input pin is the asynchronous jtag logic reset. trst# assertion causes the pci 6520 tap controller to initialize. in addition, when the tap controller is initialized, it selects the pci 6520 normal logic path (core-to-i/o). consider the following when implementing the asynchronous jtag logic reset on a board: if jtag functionality is required, one of the following should be considered: use the trst# input signal low-to-high transition once. hold the pci 6520 tms pin high while transitioning the pci 6520 tck pin five times. if jtag functionality is not required, the trst# signal must be directly connected to ground. note: ieee standard 1149.1-1990 requires pull-up resistors on the tdi, tms, and trst# pins. to remain pci r2.3-compliant, no internal pull-up resistors are provided on jtag pins in the pci 6520; therefore, the pull-up resistors must be externally added to the pci 6520 when implementing jtag.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 23-1 23?electrical specs 23 electrical specs this section presents the pci 6520 electrical specifications. 23.1 general electrical specifications the ratings provided in this subsection are those above which the useful life of the pci 6520 may be impaired. use heatsinks when operating in a pci-x 133 mhz environment. table 23-1 lists the pci 6520 maximum ratings. table 23-2 lists the pci 6520 functional operating range. table 23-3 lists the pci 6520 dc electrical characteristics. caution: stresses greater than the maximums listed in table 23-1 cause permanent damage to the pci 6520. this is a stress rating only and functional operation of the pci 6520 at or above those indicated in the operational sections of this data book is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. note: the power consumption for v dd_core and v dd_io is dependent on bus frequency, data traffic, and device loading. table 23-1. maximum ratings parameter minimum maximum parameter minimum maximum storage temperature range -55 c +125 c maximum voltage to signal pins ? 5.5v junction temperature ? +125 c maximum power ? 3.0w v dd_io supply voltage ?3.9v maximum v dd_io power (output load dependent) ?1.2w v dd_core supply voltage ?3.0v maximum v dd_core power ?1.8w analog v dd supply voltage ?3.0v maximum analog v dd power ? 50 mw table 23-2. functional operating range parameter minimum maximum parameter minimum maximum v dd_io supply voltage 3.0v 3.6v analog v dd supply voltage 1.55v 2.05v v dd_core supply voltage 1.55v 2.05v operating ambient temperature -40 c +85 c
section 23 electrical specs general electrical specifications pci 6520cb data book, version 2.0 23-2 preliminary ? 2004 plx technology, inc. all rights reserved. table 23-3. dc electrical characteristics symbol parameter condition minimum maximum unit notes v dd_io v dd_io supply voltage ? 3.0 3.6 v ? v dd_core p_a vdd s_a vdd v dd_core p_a vdd s_a vdd ?1.552.05v? v ih input high voltage ? 0.5 v dd_io v dd_io v? v il input low voltage ? -0.5 +0.3 v dd_io v? v ol output low voltage i iout = +1500 a ? +0.1 v dd_io v? v oh output high voltage i iout = -500 a 0.9 v dd_io ?v ? i il input leakage current 0 < v in < v dd_io ?2a? c in input pin capacitance ? ? 7.0 pf ?
section 23 pll and clock jitter electrical specs pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 23-3 23?electrical specs 23.2 pll and clock jitter the pci 6520 uses two plls, one for each interface. these plls can be individually disabled by connecting the p_pllen# or s_pllen# pin to 1. the minimum input frequency of each pll is 50 mhz. if a pci 6520 port is used in a low-speed application ( for example, at 33 mhz), then disable the appropriate pll by setting p_pllen# or s_pllen# to high. for typical adapter card designs, use the adapter card?s m66en pin to control the pci 6520?s primary pll by connecting the input of an inverter to the m66en pin and the output to the pci 6520?s p_pllen# input. this ensures that the primary pll is disabled when operating at 33 mhz. a similar method may be required to control the secondary pll, depending on the application. the pci 6520 uses the pci-x initialization pattern to automatically enable or disable the primary pll. pci-x r1.0b , table 6-1 (extrapolated in table 23-4), defines an add-in card?s capabilities according to its pci-xcap and m66en signal states. the primary pll is enabled or disabled when p_pllen# is pulled low, as listed in table 23-4. the pll is sensitive to power and ground noise. a dedicated set of pll power and ground pins are provided to reduce power and ground bounce caused by digital logic feeding into the plls. connect the av dd pins for each pll to a clean +1.8v supply and de-couple to the appropriate ground pins. table 23-5 details the pll operational parameters for the primary and secondary plls. table 23-4. m66en and pci-xcap encoding m66en pci-xcap conventional pci device frequency capability pci-x device frequency capability primary pll enabled ground ground 33 mhz not capable no 10k-ohm pull-down resistor pci-x 66 mhz yes not connected pci-x 133 mhz not connected ground 66 mhz not capable yes 10k-ohm pull-down resistor pci-x 66 mhz not connected pci-x 133 mhz
section 23 electrical specs pll and clock jitter pci 6520cb data book, version 2.0 23-4 preliminary ? 2004 plx technology, inc. all rights reserved. table 23-5. pll and clock jitter parameters parameter minimum typical maximum unit condition input frequency 50 ? 133 mhz ? input rise and fall time ? ? 500 ps ? input cycle-to-cycle jitter -100 ? +100 ps ? input jitter modulation frequency must be < 100 khz to allow pll tracking or > 30 mhz to allow pll filtering output cycle-to-cycle jitter -150 ? +150 ps clean power v dd = 1.8v output duty cycle 45 ? 55 % clean power v dd = 1.8v phase lock time ? ? 100 s clean power v dd = 1.8v pll power dissipation ? 9 25 mw clean power v dd = 1.8v f in = f out = 133 mhz operating ambient temperature -40 ? +85 c ?
section 23 pci/pci-x signal timing specification electrical specs pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 23-5 23?electrical specs 23.3 pci/pci-x signal timing specification figure 23-1 illustrates the pci 6520 signal timing specifications. table 23-6 delineates the minimum and maximum values, for 66 mhz pci and 133 mhz pci-x, for the symbols that appear in figure 23-1. figure 23-1. pci/pci-x signal timing specification note: refer to pci-x r1.0b for detailed descriptions of the symbols that appear in figure 23-1. v test clk output t val t su t on input t h t off valid valid table 23-6. 66 mhz pci and 133 mhz pci-x signal timing for figure 23-1 symbol parameter 66 mhz pci 133 mhz pci-x unit minimum maximum minimum maximum t val clk to signal valid delay? bused signals 2 6 0.7 3.8 ns t val(ptp) clk to signal valid delay? point to point 2 6 0.7 3.8 ns t on float to active delay 2 ? 0 ? ns t off active to float delay ? 14 ? 7 ns t su input setup time to clk? bused signals 3 ? 1.2 ? ns t su(ptp) input setup time to clk? point to point 5 ? 1.2 ? ns t h input signal hold time from clk 0 ? 0.5 ? ns v test voltage test ? 0.4 ? 0.4 v dd

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 24-1 24?mechanical specs 24 mechanical specs this section provides the pci 6520 mechanical dimensions and pinout. 24.1 mechanical dimensions the pci 6520 uses an industry standard 27 x 27 mm 380-pin (ball) pbga. figure 24-1 illustrates the mechanical dimensions. table 24-1 lists the mechanical dimensions, in millimeters, unless specified otherwise. figure 24-1. pci 6520 mechanical dimensions e e2 e3 pin a1 corner topside view underside view a2 a a1 c 0 cross-section view e1 e b pin a1 corner a b c d e f g h j k l m n p r t u v w y 2019181716151413121110987654321
section 24 mechanical specs mechanical dimensions pci 6520cb data book, version 2.0 24-2 preliminary ? 2004 plx technology, inc. all rights reserved. table 24-1. pci 6520 mechanical dimensio ns for figure 24-1 symbols (in millimeters) symbol dimension minimum nominal maximum a overall package height 2.20 2.33 2.50 a1 package standoff height ? 0.60 ? a2 encapsulation thickness 1.12 1.17 1.22 b ball diameter ? 0.75 ? c substrate thickness 0.51 0.56 0.61 e ball pitch ? 1.27 ? e overall package width 26.80 27.00 27.20 e1 ? ? 24.13 ? e2 overall encapsulation width 23.80 24.00 24.20 e3 ? 17.95 18.00 18.05 ? ? 30 ?
section 24 mechanical dimensions mechanical specs pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 24-3 24?mechanical specs this page intentionally left blank.
section 24 mechanical specs physical layout with pinout pci 6520cb data book, version 2.0 24-4 preliminary ? 2004 plx technology, inc. all rights reserved. 24.2 physical layout with pinout figure 24-2. pci 6520 physical layout with pinout?topside view (a1?a10 through y1?y10) 12345678910 a vss nc pcix100mhz nc gpio7 s_ad31 s_ad27 vss s_ad21 s_ad17 b s_req0# nc nc nc gpio6 s_ad30 s_ad26 s_cbe3# s_ad20 s_ad16 c s_req2# s_req1# vdd_io nc gpio5 s_ad29 s_ad25 s_ad23 vss s_cbe2# d s_req5# s_req4# s_req3# nc gpio4 s_ad28 s_ad24 s_ad22 s_ad19 s_frame# e s_gnt0# s_vio s_req7# s_req6# vss s_pllen# nc vdd_core s_ad18 s_irdy# f s_gnt4# s_gnt3# s_gnt2# s_gnt1# s_cr s_avss s_avdd vdd_core vdd_io vdd_io g p_vio s_gnt7# s_gnt6# s_gnt5# s_avss s_avdd vdd_core vdd_io vss vss h s_xcap_pu s_rstout# nc s_cfn# vdd_core vdd_core vdd_io j msk_in bpcc_en vss prv_dev s_clkin vdd_io vss vss vss k s_clko2 s_clko1 s_clko0 s_clkoff s_clkin_stb vdd_io vss vss vss l nc p_rstin# vdd_io s_clko4 s_clko3 vdd_io vss vss vss m gpio0 gpio1 vss gpio2 gpio3 vdd_io vss vss vss n oscsel# p_xcap pwrgd p_clkin s_xcap_in vdd_core vdd_io p p_req# refclk oscin p_gnt# p_avss p_avdd vdd_core vdd_io vss vss r p_ad29 p_ad30 vdd_io p_ad31 p_clkoe p_avss p_avdd vdd_core vdd_io vdd_io t p_ad25 p_ad26 p_ad27 p_ad28 vss p_cr p_pllen# vdd_core p_devsel# p_serr# u p_ad23 p_idsel p_cbe3# p_ad24 tms vss nc p_cbe2# p_stop# p_par v p_ad21 p_ad22 vdd_io tdi nc vdd_io p_ad18 p_frame# vss p_cbe1# w p_ad19 p_ad20 tdo dev64# vss nc p_ad17 p_irdy# p_lock# p_ad15 y vss tck trst# eepdata eepclk nc p_ad16 p_trdy# p_perr# p_ad14 12345678910
section 24 physical layout with pinout mechanical specs pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary 24-5 24?mechanical specs figure 24-3. pci 6520 physical layout with pinout?topside view (a11?a20 through y11?y20) 11 12 13 14 15 16 17 18 19 20 s_trdy# s_serr# s_ad14 s_ad10 s_ad7 s_ad4 s_ad0 s_cbe7# s_cbe5# vss a s_devsel# s_par s_ad13 s_ad9 s_ad6 s_ad3 s_ack64# s_cbe6# s_cbe4# s_ad63 b s_stop# vss s_ad12 s_ad8 vdd_io s_ad2 s_req64# vdd_io s_ad61 s_ad62 c s_lock# s_cbe1# s_ad11 s_cbe0# s_ad5 s_ad1 s_ad57 s_ad58 s_ad59 s_ad60 d s_perr# s_ad15 vdd_core s_tst1 s_tst0 vss s_ad53 s_ad54 s_ad55 s_ad56 e vdd_io vdd_io vdd_core nc nc nc s_ad50 vdd_io s_ad51 s_ad52 f vss vss vdd_io vdd_core nc s_vio s_ad46 s_ad47 s_ad48 s_ad49 g vdd_io vdd_core vdd_core s_ad42 s_ad43 s_ad44 s_ad45 h vss vss vss vdd_io s_ad38 s_ad39 vss s_ad40 s_ad41 j vss vss vss vdd_io s_ad33 s_ad34 s_ad35 s_ad36 s_ad37 k vss vss vss vdd_io s_m66en nc s_clkrun# s_par64 s_ad32 l vss vss vss vdd_io p_par64 p_clkrun# vss nc p_m66en m vdd_io vdd_core vdd_core p_ad35 p_ad34 p_ad33 p_ad32 n vss vss vdd_io vdd_core nc p_vio p_ad39 p_ad38 p_ad37 p_ad36 p vdd_io vdd_io vdd_core nc nc nc p_ad42 vdd_io p_ad41 p_ad40 r p_ad13 p_ad8 vdd_core p_tst1 p_tst0 vss p_ad46 p_ad45 p_ad44 p_ad43 t p_ad12 p_cbe0# p_ad5 p_ad1 p_cbe7# p_cbe4# p_ad60 p_ad54 p_ad48 p_ad47 u p_ad11 vss p_ad4 p_ad0 vdd_io p_ad63 p_ad59 vdd_io p_ad51 p_ad49 v p_ad10 p_ad7 p_ad3 p_ack64# p_cbe6# p_ad62 p_ad58 p_ad55 p_ad52 p_ad50 w p_ad9 p_ad6 p_ad2 p_req64# p_cbe5# p_ad61 p_ad57 p_ad56 p_ad53 vss y 11 12 13 14 15 16 17 18 19 20

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary a-1 a?using pci 6520 a using pci 6520 figure a-1. pci 6520 internal architecture serial eeprom interface clock buffers gpi os internal bus arbiter reset upstream buffers posted write fifo 4 entries delayed transaction fifo 4 entries flow-through control delayed transaction fifo 4 entries posted write fifo 4 entries downstream buffers configuration space upstream downstream primary bus secondary bus
appendix a using pci 6520 application pci 6520cb data book, version 2.0 a-2 preliminary ? 2004 plx technology, inc. all rights reserved. a.1 application because the pci 6520 primary and secondary ports are asynchronous to one another, these two independent systems can run at differing frequencies. the secondary bus can be run faster than the primary bus, and vice versa. the pci 6520 can be set to enforce pci-x protocol, without requiring standard pci-x reset initialization. the pci 6520 controls powerful programmable buffers, which can be used to regulate data throughput for multiple pci masters on the secondary port. the pci 6520 can be programmed to prefetch up to 2 kb at a time and the data can be stored in the fifo. the host system pci-x bus is connected to the pci 6520 primary port. the secondary pci port can use a custom-designed external arbiter or the pci 6520 internal arbiter. to provide clocks to secondary pci devices and pci 6520 s_clkin, use custom-designed clock generations, pci 6520 s_clko[4:0] outputs (derived out of the primary port pci clock input), or an external oscillator. the pci 6520 also supports private pci devices on the secondary bus. by setting prv_dev to 1, the pci 6520 allows secondary port idsel re-routing, using s_ad[23:16] to s_ad24. when s_ad24 has no device connected to it, s_ad[23:16] type 1 access cycles are master aborted. by setting prv_dev to 1, and programming the corresponding special memory range registers, the pci 6520 also reserves a private memory region for secondary port private device use only. the pci 6520 does not respond to accesses to this private region by primary or secondary pci masters. figure a-2 provides basic optimization design. figure a-2. pci 6520 basic optimization design s-port pci 6520 p-port host system backplane secondary bus pci/pci-x devices + private devices prv_dev = optional 0 or 1 s_cfn# = optional 0 or 1 s_clko[4:0] = use optional s_rstout# = used enforce pci-x: pci 6520 has a p_xcap input pin to enforce pci-x protocol without requiring standard pci-x reset initialization
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary b-1 b?pci-x clock & frequency initialization sequence b pci-x clock and frequency initialization sequence b.1 bus speed and type detection figure b-1 provides an example of a complex programmable logic device (cpld) being used to detect bus type and speed, and feed to the pci 6520 during the reset phase. figure b-1. cpld used to detect bus type and speed and feed to pci 6520 during reset phase cpld clock generator primary pci reset m66en# pci-xcap s_clkoff sclk_in sclko_0 clko_ n clko_1 pci 6520 s_rstout# clko_0 pci 6520 p_rstin# pci 6520 pcix100mhz pci 6520 s_xcap_pu pci 6520 s_xcap_in s_m66en# oe# backplane clock buffer pci 6520
appendix b pci-x clock and frequency initialization sequence secondary clock outputs pci 6520cb data book, version 2.0 b-2 preliminary ? 2004 plx technology, inc. all rights reserved. b.2 secondary clock outputs note: secondary clocks from the pci 6520 are not recommended for pci-x use. use high-quality clock buffers for pci-x applications. a high-quality clock generator and clock buffer should be used for 100 and 133 mhz pci-x applications. all clocks must have similar flight time, no matter whether they are connected to secondary port pci-x devices or used for feedback to the pci 6520 ( that is , all clock traces are to be of similar length or delay compensated). b.3 internal clock divider the pci 6520 internal clock divider works with only with conventional pci applications. do not use the divider for pci-x applications.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary c-1 c?6520/6540 pin comparison c pci 6520cb and pci 6540cb pin comparison note: nc = no connect pins. table c-1. pci 6520cb versus pci 6540cb pin assignment comparison pin location pci 6520cb pci 6540cb a2 nc gpio15 a3 pcix100mhz gpio13 a4 nc gpio10 a8 v ss s_idsel b2 nc gpio14 b3 nc gpio12 b4 nc gpio9 c4 nc gpio8 d4 nc gpio11 f15 nc slpcix h3 nc s_rstin# l1 nc p_rstout# l17 nc s_pme# m19 nc p_pme# u6 v ss eject u7 nc p_boot v5 nc trans# w5 v ss u_mode w6 nc l_stat y6 nc enum#

pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary d-1 d?ordering d general information the plx fastlane pci 6520 is a 64-bit, 133 mhz pci-x-to-pci-x bridge that supports transparent operation. the pci 6520 provides a range of added- value features to system designers, including: two pci-x ports, each capable of running at the full 64-bit, 133 mhz speed asynchronous primary and secondary ports 5v tolerant i/o programmable prefetch programmable flow through zero wait state burst 10-kb data fifo five secondary clock outputs reference clock input for frequency detection pci power management support arbitration support for eight secondary bus masters serial eeprom for configuration 8 general purpose i/o pins vital product data (vpd) support jtag boundary scan the pci 6520 is offered in an industry-standard 27 x 27 mm 380-pin (ball) pbga, and is designed to operate over the industrial temperature range. d.1 package ordering table d-1. available package package ordering part number 380-pin pbga PCI6520-CB13BI pci 6520-cb13bi pci 6520?family/core pci 6520 device cb ?part revision code 13?speed grade ( 133 mhz pci-x bus) b?package type b = plastic ball grid array c?case temperature i = industrial temperature c = commercial temperature es = engineering sample
appendix d general information united states and international representatives, and distributors pci 6520cb data book, version 2.0 d-2 preliminary ? 2004 plx technology, inc. all rights reserved. d.2 united states and international representatives, and distributors a list of plx technology, inc., representatives and distributors can be found at http://www.plxtech.com. d.3 technical support plx technology, inc., technical support information is listed at http://www.plxtech.com/support/, or call 408 774-9060 or 800 759-3735.
pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary index-1 index index a abnormal response 8-16 termination 13-2, 17-2 abort master 3-9, 3-11, 3-21, 6-5, 6-10, 6-15, 6-16, 6-32, 6-35, 8-9, 8-11, 8-12, 8-13, 8-15, 8-16, 8-18, 9-1, 9-3, 9-4, 9-10, 9-12, 9-17, 9-18, 9-19, 10-5, 12-13, 13-2, 17-1, 17-2, a-2 target 3-9, 6-5, 6-10, 6-15, 6-32, 6-35, 8-3, 8-4, 8-7, 8-12, 8-13, 8-14, 8-15, 8-16, 8-18, 9-3, 9-5, 9-9, 9-10, 9-17, 9-18, 9-19, 9-20, 12-1, 12-4, 12-13, 13-2 access, exclusive 13-1?13-2 acntrl register 6-17, 6-28, 14-1, 14-2 adb 9-5?9-22, 19-2 address decoding 10-1?10-5 allowable disconnect boundary see adb arbiter control register 6-2, 6-17, 14-1 arbitration 1-5, 3-11, 3-13, 6-27?6-28, 9-3, 14-1?14-3, d-1 architectural boundary scan see ieee standard attributes 9-1, 9-2, 9-4, 9-5, 9-7?9-8, 9-9, 9-10, 9-12, 9-12?9-14, 9-15, 9-20?9-21 relaxed ordering bit 11-4, 11-6 b bcntrl register 4-3, 5-4, 6-4, 6-14?6-15, 6-17, 6-19, 8-8, 10-1, 10-4, 19-3 boundary scan description language 22-2 pins 3-3, 3-19, 22-1, 22-2 bpcc_en 3-21, 5-5, 20-1 bridge behavior 17-1?17-2 control register 6-2, 6-14?6-15 pci 6000 series 1-1?1-4 pci-x status register 6-3, 6-52 supports extension register 6-3, 6-48 bsdl see boundary scan description language bufcr register 6-27, 6-40, 19-3 buffer control register 6-2, 6-27 buffering multiple write transactions 8-5 buffers adb size 9-5 i/o 22-2 bus operation pci 8-1?8-18 pci-x 9-1?9-22 c cap_ptr register 6-5, 6-14 ccntrl register 3-21, 6-16, 6-37, 8-5, 10-5 chip control register 3-21, 6-2, 6-16, 6-37, 8-5 clkcntrl register 3-3, 3-15, 3-16, 3-17, 4-1, 4-3, 5-3, 6-34 clkrun register 6-36 clock control register 4-1, 5-3, 6-34 clock, pci-x b-1?b-2 clocking 4-1?4-6 clock-related pins 3-3, 3-15?3-17 commands 16-1?16-4 conventional pci-to-pci-x 9-21 pci-x-to-conventional pci 9-22 primary 3-7, 6-2 primary pci register 6-4 read queue 2-2 secondary 3-11 serial eeprom 7-1 completion delayed read 8-7?8-8 delayed write 11-2 split 9-1?9-20 control registers 4-1, 5-3, 6-16?6-17, 6-34, 8-6 controller, test access port (tap) see test access port controller d dac 3-6, 3-10, 8-1, 8-2, 9-2, 9-6, 9-10, 9-11, 9-20, 16-2, 16-4 dcntrl register 5-4, 6-17 deadlock 11-1, 11-2, 11-4?11-6 debug 22-1?22-2 decoding 10-1?10-5 de-coupling, power supply 3-5 delayed read 8-5, 8-7?8-8, 8-16, 13-1, 18-1 delayed read or write 3-9, 6-18, 6-20, 6-26, 6-32, 6-35, 8-2, 8-3, 8-5, 8-12, 8-13, 8-15, 8-17, 8-18, 11-1, 11-2, 11-2?11-3, 12-3, 12-13 dev64# 3-21, 5-5, 6-29, 6-52 diagnostic control register 5-3, 6-17 dual address cycle see dac
ecp to p_ad[63:32] pci 6520cb data book, version 2.0 index-2 preliminary ? 2004 plx technology, inc. all rights reserved. e ecp 20-1 eepaddr register 6-30, 7-1 eepclk 3-19, 5-5, 7-1 eepcntrl register 6-29, 7-1 eepdata pin 3-19, 5-5, 7-1 eepdata register 6-30, 7-1 electrical specs 23-1 enhanced capabilities port see ecp error handling 12-1?12-13 exclusive access 13-1?13-2 extended registers 5-2, 5-7, 6-3, 6-41 extrdata register 5-7, 6-40, 6-41 extridx register 5-7, 6-40, 6-41, 6-42, 6-43 f fifos 1-5, 6-21, 8-6, 8-7, 11-2, 11-3, 12-1, 12-4, 18-1? 18-3, 19-1?19-4, a-2 fixed-priority scheme 14-2?14-3 flow-through 18-1?18-3 primary 6-2, 6-18, 7-3, 18-1, 18-2 secondary 6-2, 6-26, 7-3 frame# 17-2 g gpio interface 15-1 gpio[3:0] pins 3-20, 4-1?4-3 gpio[7:0] pins 3-3, 5-5 gpio[7:4] pins 3-20 gpioid[3:0] register 6-33, 15-1 gpioid[7:4] register 6-39, 15-1 gpiood[3:0] register 6-33, 15-1 gpiood[7:4] register 6-39, 15-1 gpiooe[3:0] register 3-20, 6-33, 15-1 gpiooe[7:4] register 3-20, 6-39, 15-1 ground pins 3-24, 4-4, 23-3 h hardware 22-1 header registers, pci type 1 6-4?6-15, 7-3 i iacntrl register 6-28, 7-3, 14-1, 14-2, 14-3 ieee standard 1149.1-1990 22-1?22-2 ieee standard test access port and boundary-scan architecture see ieee standard 1149.1-1990 incremental prefetch count 6-2, 6-24, 7-3, 18-3 initialization 5-1?5-7 interface debug 22-1?22-2 gpio 15-1 jtag 22-1?22-2 primary 12-6, 16-1?16-2 secondary 12-6, 16-3?16-4 internal arbiter control register 6-2, 6-27, 6-28, 7-3, 14-1, 14-2 irdy# 17-2 isa 6-14, 10-1, 10-4 j jtag 22-1?22-2 pins 3-3, 3-19 l locks 13-1?13-2 m m66en 4-5, 23-3 master abort see abort, master mechanical specs 24-1?24-4 memory prefetchable 6-12?6-13, 10-3 private 6-2, 6-16, 6-37, 10-5, a-2 write and invalidate 6-4, 6-6, 6-21, 8-1, 8-2, 8-3, 8-12, 8-14, 9-21, 11-1, 16-2, 16-4 miscellaneous options register 6-2, 6-20?6-21, 7-3, 8-3, 8-9 miscellaneous pins 3-3, 3-21?3-23 mscopt register 3-9, 3-14, 6-20?6-21, 7-3, 8-3, 8-9, 11-2, 13-2 msk_in 3-3, 3-15, 4-1?4-3, 5-5 n nc 3-24 no connect pins 3-24 normal termination vs. master abort 8-12, 8-13 o optimization basic design a-2 flow-through 18-1?18-3 ordering, transaction 11-1?11-6 oscin 3-3, 3-15, 4-4, 5-2, 5-5 oscsel# 3-3, 3-15, 4-4, 5-5 p p_ack64# 3-2, 3-6, 5-5 p_ad[31:0] 3-6, 16-2 p_ad[63:0] 3-2, 5-5 p_ad[63:32] 6-38
p_av dd to pcixbsr register pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary index-3 index p_av dd 3-24, 4-4, 5-5, 23-3 p_av ss 3-24, 5-5 p_cbe[3:0]# 3-6, 8-2, 8-9, 16-1?16-2 p_cbe[7:0]# 3-2, 5-5 p_cbe[7:4]# 3-7, 6-38, 8-9 p_clkin 3-3, 3-15, 4-1, 4-4, 4-6, 5-2, 5-3, 5-5, 6-31 p_clkoe 3-3, 3-15, 5-6, 6-29 p_clkrun# 3-21, 5-6 p_cr 3-3, 3-15, 5-6 p_devsel# 3-2, 3-7, 5-6, 8-8, 12-1, 17-1, 17-2 p_frame# 3-2, 3-7, 5-6, 13-2 p_gnt# 3-2, 3-7, 5-6, 14-1 p_idsel 3-2, 3-7, 5-6, 8-8, 16-2 p_irdy# 3-2, 3-7, 5-6, 6-26 p_lock# 3-2, 3-7, 5-6, 13-1?13-2 p_m66en 3-2, 3-8, 3-15, 4-4, 5-2, 5-6 p_par 3-2, 3-8, 5-6, 14-1 p_par64 3-2, 3-8, 5-6, 6-38, 14-1, 17-2 p_perr# 3-2, 3-8, 5-6, 12-1?12-13 p_pllen# 3-3, 3-15, 4-4, 5-6, 23-3 p_req# 3-2, 3-8, 5-6, 14-1 p_req64# 3-2, 3-9, 5-6 p_rstin# 3-18, 4-1, 5-2, 5-4, 5-5?5-6, 7-1, 9-1 p_serr# 3-2, 3-9, 5-6, 6-2, 6-5, 6-15, 6-32, 6-35, 8-4, 8-7, 8-8, 8-13, 8-14, 8-15, 8-16, 12-1?12-13, 13-2, 17-2 p_stop# 3-2, 3-9, 5-6 p_trdy# 3-2, 3-10, 5-6 p_tst[1:0] 3-21, 5-6 p_v io 3-4, 3-24, 5-5 p_xcap 3-22, 5-1, 5-6 package specs 24-1?24-4 parity 12-1?12-13 error rules 9-4 primary signal 3-8 reporting errors 17-2 secondary signal 3-12, 3-13 pbga industry standard 24-1 package ordering information d-1 pinout 24-4?24-5 pci 6520 general product information 1-1?1-6, d-1 pci arbitration 14-1?14-3 pci bus operation 8-1?8-18 pci bus power management interface specification, revision 1.1 see pci power mgmt. r1.1 pci configuration registers 6-2?6-53 pci local bus specification, revision 2.3 see pci r2.3 pci power mgmt. r1.1 2-1, 20-1 pci r2.3 1-5, 3-2, 5-2, 11-3, 21-1, 22-2 pci to pci bridge architecture specification, revision 1.2 see p-to-p bridge r1.2 pci transactions 8-1?8-18, 11-1?11-3 pci type 1 header registers 6-4?6-15 pcibistr register 6-7, 7-3 pciccr register 6-6, 6-38 pciclsr register 6-6, 6-22, 6-23, 8-3, 18-1 pcicr register 6-4?6-5, 6-10, 6-14, 6-15, 6-32, 7-3, 8-4, 8-7, 8-13, 8-14, 8-15, 8-16, 10-1, 10-2, 10-4, 10-5, 12-1, 12-4, 12-6?12-13, 13-2, 17-2 pcihtr register 6-7, 6-38, 7-3 pciidr register 6-4, 6-38, 7-3 pciiobar register 6-9, 6-14, 10-1, 10-2 pciiobaru16 register 6-9, 6-13, 10-2 pciiolmt register 6-9, 10-2 pciiolmtu16 register 6-9, 6-13, 10-2 pciipr register 6-14 pciltr register 6-6 pcimbar register 6-11, 10-2, 10-3 pcimlmt register 6-11, 10-2, 10-3 pcipbno register 6-8, 8-11 pcipmbar register 6-12, 6-13, 10-2, 10-4 pcipmbaru32 register 6-12, 6-13, 10-2 pcipmlmt register 6-12, 6-13, 10-2, 10-4 pcipmlmtu32 register 6-12, 6-13, 10-2 pcirev register 6-6 pcisbno register 6-8, 8-9, 8-11 pcisltr register 6-8 pcisr register 6-5, 8-13, 8-14, 8-15, 8-16, 12-1, 12-2, 12-4, 12-6, 12-8, 12-13, 17-1 pcissr register 6-10, 8-13, 8-14, 8-15, 8-16, 12-1, 12-4, 12-7, 12-9, 12-13, 17-1 pcisubno register 6-8, 8-11 pci-x addendum to pci local bus specification, revision 1.0b see pci-x r1.0b pci-x bus operation 9-1?9-22 pci-x capability registers 6-50?6-53 pci-x clock b-1?b-2 pci-x r1.0b 3-2, 3-3, 6-1, 11-4, 23-5 pci-x transactions 9-1?9-22, 11-4?11-6 pcix_next register 6-50 pcix100mhz 3-20, 5-1, 5-5 pcixbsr register 3-21, 6-52, 9-8, 9-12, 9-14
pcixcapid register to pins pci 6520cb data book, version 2.0 index-4 preliminary ? 2004 plx technology, inc. all rights reserved. pcixcapid register 6-50 pcixdnstr register 6-51, 6-53, 19-2 pcixssr register 3-20, 6-50?6-51 pcixupstr register 6-52, 6-53, 19-4 pftcr register 6-18, 7-3, 18-1, 18-2 philips 74f166 4-2?4-3 physical specs 24-1?24-4 pin states, during pwrgd and primary reset 5-5?5-6 pincpcnt register 6-22, 6-24, 7-3, 18-1, 18-3, 19-2, 19-4 pinout 3-6?3-24 pbga 24-4?24-5 specs 24-1?24-4 pins boundary scan 3-3, 3-19, 22-1, 22-2 bpcc_en 3-21, 5-5, 20-1 clock related 3-3, 3-15?3-17 dev64# 3-21, 5-5, 6-29, 6-52 eepclk 3-19, 5-5, 7-1 eepdata 3-19, 5-5, 7-1 frame# 17-2 gpio[3:0] 3-20, 4-1?4-3 gpio[7:0] 3-3, 5-5 gpio[7:4] 3-20 ground 3-24, 4-4, 23-3 irdy# 17-2 jtag 3-3, 3-19, 22-1 m66en 4-5, 23-3 miscellaneous 3-3, 3-21?3-23 msk_in 3-3, 3-15, 4-1?4-3, 5-5 nc 3-24 no connect 3-24 oscin 3-3, 3-15, 4-4, 5-2, 5-5 oscsel# 3-3, 3-15, 4-4, 5-5 p_ack64# 3-2, 3-6, 5-5 p_ad[31:0] 3-6, 16-2 p_ad[63:0] 3-2, 5-5 p_ad[63:32] 6-38 p_av dd 3-24, 4-4, 5-5, 23-3 p_av ss 3-24, 5-5 p_cbe[3:0]# 3-6, 8-2, 8-9, 16-1?16-2 p_cbe[7:0]# 3-2, 5-5 p_cbe[7:4]# 3-7, 6-38, 8-9 p_clkin 3-3, 3-15, 4-1, 4-4, 4-6, 5-2, 5-3, 5-5, 6-31 p_clkoe 3-3, 3-15, 5-6, 6-29 p_clkrun# 3-21, 5-6 p_cr 3-3, 3-15, 5-6 p_devsel# 3-2, 3-7, 5-6, 8-8, 12-1, 17-1, 17-2 p_frame# 3-2, 3-7, 5-6, 13-2 p_gnt# 3-2, 3-7, 5-6, 14-1 p_idsel 3-2, 3-7, 5-6, 8-8, 16-2 p_irdy# 3-2, 3-7, 5-6, 6-26 p_lock# 3-2, 3-7, 5-6, 13-1?13-2 p_m66en 3-2, 3-8, 3-15, 4-4, 5-2, 5-6 p_par 3-2, 3-8, 5-6, 14-1 p_par64 3-2, 3-8, 5-6, 6-38, 14-1, 17-2 p_perr# 3-2, 3-8, 5-6, 12-1?12-13 p_pllen# 3-3, 3-15, 4-4, 5-6, 23-3 p_req# 3-2, 3-8, 5-6, 14-1 p_req64# 3-2, 3-9, 5-6 p_rstin# 3-18, 3-20, 4-1, 5-2, 5-4, 5-5?5-6, 7-1, 9-1, 15-1 p_serr# 3-2, 3-9, 5-6, 6-2, 6-5, 6-15, 6-32, 6-35, 8-4, 8-7, 8-8, 8-13, 8-14, 8-15, 8-16, 12-1?12-13, 13-2, 17-2 p_stop# 3-2, 3-9, 5-6 p_trdy# 3-2, 3-10, 5-6 p_tst[1:0] 3-21, 5-6 p_v io 3-4, 3-24, 5-5 p_xcap 3-22, 5-1, 5-6 pcix100mhz 3-20, 5-1, 5-5 power 3-24, 4-4, 23-3 primary clock 3-3, 3-15, 3-21, 4-1, 4-6, 5-2, 20-1 primary pci bus interface 3-2, 3-6?3-10 prv_dev 3-21, 5-6, 6-16, 6-37, 10-5, a-2 pwrgd 3-18, 5-2?5-6, 5-7 refclk 3-3, 3-15, 4-6, 5-5 reset 3-3, 3-18 s_ack64# 3-2, 3-10, 5-5 s_ad[31:0] 3-10, 16-4 s_ad[63:0] 3-2, 5-5 s_ad[63:32] 3-10, 6-38 s_av dd 3-24, 4-4, 5-5, 23-3 s_av ss 3-24, 5-5 s_cbe[3:0]# 3-11, 16-3?16-4 s_cbe[7:0]# 3-2, 5-5 s_cbe[7:4]# 3-11, 6-38 s_cfn# 3-22, 5-5, 6-29, 14-1 s_clkin 3-3, 3-16, 4-1, 4-3, 4-4, 4-6, 5-5, 6-29, 6-31, a-2 s_clkin_stb 3-3, 3-16, 4-4, 5-5 s_clko[4:0] 4-1?4-4, 5-5, 6-48 s_clko[4:1] 3-3, 3-16, 3-17, 4-1 s_clko0 3-3, 3-16, 3-17, 6-34, b-2 s_clkoff 3-3, 3-17, 4-1, 5-5 s_clkrun# 3-22, 5-5, 6-36 s_cr 3-3, 3-17, 5-5 s_devsel# 3-2, 3-11, 5-3, 5-5, 12-1, 17-1, 17-2 s_frame# 3-2, 3-11, 5-5, 13-2, 14-2, 14-3 s_gnt[7:0]# 3-2, 5-6, 14-1 s_gnt[7:1]# 3-12, 14-1 s_gnt0# 3-11, 14-1, 14-3 s_idsel 10-5 s_irdy# 3-2, 3-12, 5-6, 6-18, 14-3 s_lock# 3-2, 3-12, 5-6, 13-1?13-2 s_m66en 3-2, 3-12, 4-4, 5-1, 5-2, 5-6
pitlpcnt register to registers pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary index-5 index s_par 3-2, 3-12, 5-6, 14-3 s_par64 3-2, 3-13, 5-6, 6-38, 14-3, 17-2 s_perr# 3-2, 3-13, 5-6, 6-10, 12-1?12-13 s_pllen# 3-17, 4-4, 5-6, 23-3 s_req[7:0]# 3-2, 5-6, 6-17, 14-1 s_req[7:1]# 3-13, 14-1 s_req0# 3-13, 14-1, 14-3 s_req64# 3-2, 3-14, 5-6 s_rstout# 3-18, 4-3, 4-4, 5-2, 5-3, 5-4, 5-6, 6-15, 6-17, 6-51, 20-1 s_serr# 3-2, 3-14, 6-14, 12-1, 12-5, 12-12?12-13 s_stop# 3-2, 3-14, 5-3, 5-6 s_trdy# 3-2, 3-14, 5-3, 5-6 s_tst[1:0] 3-22, 5-6 s_v io 3-4, 3-24, 5-6 s_xcap_in 3-23, 5-1, 5-6, 9-1 s_xcap_pu 3-23, 5-1, 5-6 secondary clock 3-3, 3-16, 3-17, 3-21, 3-22, 4-1, 4-4, 4-6, 5-2, 20-1 secondary pci bus interface 3-2, 3-10?3-14 serial eeprom 3-3, 3-19 tck 3-19, 22-1 tdi 3-19, 22-1, 22-2 tdo 3-19, 22-1, 22-2 tms 3-19, 22-1 trst# 3-19, 22-1, 22-2 v dd_core 3-24, 5-6 v dd_io 3-24, 5-6 v ss 3-15, 3-17, 3-24, 5-6 see also pinout designations and appendix c, pci 6520cb and pci 6540cb pin comparison pitlpcnt register 6-22, 6-24, 7-3, 18-1, 18-2, 19-2, 19-4 plx technology, inc. product information 1-1 product ordering and technical support d-2 pmaxpcnt register 6-25, 6-27, 7-3, 18-1, 18-3, 19-3 pmc register 6-38, 6-46, 6-47, 7-3 pmcapid register 6-46 pmcdata register 6-38, 6-48, 7-3 pmcsr register 5-4, 6-3, 6-38, 6-48, 7-3, 20-1 pmcsr_bse register 6-48 pmnext register 6-46 power dissipation 1-2?1-3, 3-4, 4-1, 4-5, 23-1, 23-4 power good input signal 3-18 reset 5-2?5-3 see also pwrgd power management 20-1 power management capability registers 6-3, 6-46?6-48, 7-3 power pins 3-24, 4-4, 23-3 power supply 3-5 prefetch 18-3 data timeout flushing 19-3 incremental count 6-2, 6-24, 7-3 memory 6-12?6-13, 10-3 read transaction 8-5?8-6 reprogramming registers 18-1 setting byte count 19-4 smart 6-27, 6-40?6-45, 19-3 prefetch control registers 6-2, 6-22?6-25, 7-3, 18-1, 18-2, 19-2, 19-4 primary clock frequency measurement 4-6 clock pins 3-3, 3-15, 3-21, 4-1, 4-6, 5-2, 20-1 flow-through control registers 6-18 pci bus interface pins 3-2, 3-6?3-10 priority schemes 14-2?14-3 private memory 6-2, 6-16, 6-37, 10-5, a-2 prv_dev 3-21, 5-6, 6-16, 6-37, 10-5, a-2 pserred register 6-32, 8-13?8-16, 12-1, 12-3 pserrsr register 6-35, 12-1 p-to-p bridge r1.2 6-1, 10-3, 12-13 pull-up/pull-down resistor recommendations 3-2?3-4 pvpd_next register 6-49 pvpdad register 6-49 pvpdata register 6-49 pvpdid register 6-49 pvtmbar register 3-21, 6-16, 6-37 pvtmbaru32 register 3-21, 6-37 pvtmlmt register 3-21, 6-37 pvtmlmtu32 register 6-37 pwrgd 3-18, 5-2?5-6, 5-7 r read-only control register 6-38 refclk 3-3, 3-15, 4-6, 5-5 registers acntrl 6-17, 6-28, 14-1, 14-2 arbiter control 6-2, 6-17, 14-1 bcntrl 4-3, 5-4, 6-4, 6-14?6-15, 6-17, 6-19, 8-8, 10-1, 10-4, 19-3 bufcr 6-27, 6-40, 19-3 buffer control 6-2, 6-27 cap_ptr 6-5, 6-14 ccntrl 3-21, 6-16, 6-37, 8-5, 10-5 chip control 3-21, 6-2, 6-16, 6-37, 8-5 clkcntrl 3-3, 3-15, 3-16, 3-17, 4-1, 4-3, 5-3, 6-34 clkrun 6-36 clock control 3-15, 3-16, 4-1, 4-3, 5-3, 6-34 control 3-15, 3-16, 4-1, 4-3, 5-3, 6-16?6-17, 6-28, 6-34, 6-37, 8-6 dcntrl 5-4, 6-17 diagnostic control 5-3, 6-17
reset to rotating-priority scheme pci 6520cb data book, version 2.0 index-6 preliminary ? 2004 plx technology, inc. all rights reserved. eepaddr 6-30, 7-1 eepcntrl 6-29, 7-1 eepdata 6-30, 7-1 extended 5-2, 5-7, 6-3, 6-41 extrdata 5-7, 6-40, 6-41 extridx 5-7, 6-41, 6-42, 6-43 gpioid[3:0] 6-33, 15-1 gpioid[7:4] 6-39, 15-1 gpiood[3:0] 6-33, 15-1 gpiood[7:4] 6-39, 15-1 gpiooe[3:0] 3-20, 6-33, 15-1 gpiooe[7:4] 3-20, 6-39, 15-1 header, pci type 1 6-4?6-15, 7-3 iacntrl 6-28, 7-3, 14-1, 14-2, 14-3 internal arbiter control 6-2, 6-28, 7-3, 14-1, 14-2 miscellaneous options 6-2, 6-20?6-21, 7-3, 8-3 mscopt 3-9, 3-14, 6-20?6-21, 7-3, 8-3, 8-9, 11-2, 13-2 pci configuration 6-2?6-53 pci type 1 header 6-4?6-15 pcibistr 6-7, 7-3 pciccr 6-6, 6-38 pciclsr 6-6, 6-22, 6-23, 8-3, 18-1 pcicr 6-4?6-5, 6-10, 6-14, 6-15, 6-32, 7-3, 8-4, 8-7, 8-13, 8-14, 8-15, 8-16, 10-1, 10-2, 10-4, 10-5, 12-1, 12-4, 12-6?12-13, 13-2, 17-2 pcihtr 6-7, 6-38, 7-3 pciidr 6-4, 6-38, 7-3 pciiobar 6-9, 6-14, 10-1, 10-2 pciiobaru16 6-9, 6-13, 10-2 pciiolmt 6-9, 10-2 pciiolmtu16 6-9, 6-13, 10-2 pciipr 6-14 pciltr 6-6 pcimbar 6-11, 10-2, 10-3 pcimlmt 6-11, 10-2, 10-3 pcipbno 6-8, 8-11 pcipmbar 6-12, 6-13, 10-2, 10-4 pcipmbaru32 6-12, 6-13, 10-2 pcipmlmt 6-12, 6-13, 10-2, 10-4 pcipmlmtu32 6-12, 6-13, 10-2 pcirev 6-6 pcisbno 6-8, 8-9, 8-11, 9-12 pcisltr 6-8 pcisr 6-5, 8-13, 8-14, 8-15, 8-16, 12-1, 12-2, 12-4, 12-6, 12-8, 12-13, 17-1 pcissr 6-10, 8-13, 8-14, 8-15, 8-16, 12-1, 12-4, 12-7, 12-9, 12-13, 17-1 pcisubno 6-8, 8-11 pcix_next 6-50 pcixbsr 3-21, 6-52, 9-8, 9-12, 9-14 pcixcapid 6-50 pcixdnstr 6-51, 6-53, 19-2 pcixssr 3-20, 6-50?6-51 pcixupstr 6-52, 6-53, 19-4 pftcr 6-18, 7-3, 18-1, 18-2 pincpcnt 6-22, 6-24, 7-3, 18-1, 18-3, 19-2, 19-4 pitlpcnt 6-22, 6-24, 7-3, 18-1, 18-2, 19-2, 19-4 pmaxpcnt 6-25, 6-27, 7-3, 18-1, 18-3, 19-3 pmc 6-38, 6-46, 6-47, 7-3 pmcapid 6-46 pmcdata 6-38, 6-48, 7-3 pmcsr 5-4, 6-3, 6-38, 6-48, 7-3, 20-1 pmcsr_bse 6-48 pmnext 6-46 power management capability 6-3, 6-46?6-48, 7-3 prefetch control 6-22?6-25, 7-3, 18-1, 18-2, 19-2, 19-4 primary flow-through control 6-18 pserred 6-32, 8-13?8-16, 12-1, 12-3 pserrsr 6-35, 12-1 pvpd_next 6-49 pvpdad 6-49 pvpdata 6-49 pvpdid 6-49 pvtmbar 3-21, 6-16, 6-37 pvtmbaru32 3-21, 6-37 pvtmlmt 3-21, 6-37 pvtmlmtu32 6-37 read-only control 6-38 rrc 6-3, 6-38, 6-46, 14-3 secondary flow-through control 6-2, 6-26, 7-3 serial eeprom 5-7, 6-29?6-30 sftcr 6-26, 7-3, 18-1, 18-2 sincpcnt 6-23, 6-24, 7-3, 18-1, 18-3, 19-2, 19-4 sitlpcnt 6-23, 6-24, 7-3, 18-1, 18-2, 19-2, 19-4 smaxpcnt 6-24, 6-25, 6-27, 7-3, 18-1, 18-3, 19-3 spubard x registers 6-43?6-45 spul32bar1 6-41 spul32bar2 6-42 spul32bar3 6-43 spuu32bar1 6-42 spuu32bar2 6-42 spuu32bar3 6-43 system error event 6-32 test 6-29 timeout control 6-2, 6-19, 7-3, 8-4 timer 4-6, 6-15, 6-31 tmrcnt 4-6, 6-31 tmrcntrl 4-6, 6-31 tocntrl 6-19, 6-32, 7-3, 8-4 vpd 2-1, 6-49, 21-1 reset 5-1?5-7 jtag 22-1, 22-2 pins 3-3, 3-18 reset input effect 5-4 resistor recommendations, pull-up/pull-down 3-2?3-4 rotating-priority scheme 14-2
rrc register to test access port controller pci 6520cb data book, version 2.0 ? 2004 plx technology, inc. all rights reserved. preliminary index-7 index rrc register 6-3, 6-38, 6-46, 14-3 rstin# 3-20, 15-1 rules deadlock avoidance 11-5 pci-x bus, general 9-1?9-4 transaction ordering, conventional pci 11-1?11-3 transaction ordering, pci-x 11-5 s s_ack64# 3-2, 3-10, 5-5 s_ad[31:0] 3-10, 16-4 s_ad[63:0] 3-2, 5-5 s_ad[63:32] 3-10, 6-38 s_av dd 3-24, 4-4, 5-5, 23-3 s_av ss 3-24, 5-5 s_cbe[3:0]# 3-11, 16-3?16-4 s_cbe[7:0]# 3-2, 5-5 s_cbe[7:4]# 3-11, 6-38 s_cfn# 3-22, 5-5, 6-29, 14-1 s_clkin 3-3, 3-16, 4-1, 4-3, 4-4, 4-6, 5-5, 6-29, 6-31, a-2 s_clkin_stb 3-3, 3-16, 4-4, 5-5 s_clko[4:0] 4-1?4-4, 5-5, 6-48 s_clko[4:1] 3-3, 3-16, 3-17, 4-1 s_clko0 3-3, 3-16, 3-17, 6-34, b-2 s_clkoff 3-3, 3-17, 4-1, 5-5 s_clkrun# 3-22, 5-5, 6-36 s_cr 3-3, 3-17, 5-5 s_devsel# 3-2, 3-11, 5-3, 5-5, 12-1, 17-1, 17-2 s_frame# 3-2, 3-11, 5-5, 13-2, 14-2, 14-3 s_gnt[7:0]# 3-2, 5-6, 14-1 s_gnt[7:1]# 3-12, 14-1 s_gnt0# 3-11, 14-1, 14-3 s_idsel 10-5 s_irdy# 3-2, 3-12, 5-6, 6-18, 14-3 s_lock# 3-2, 3-12, 5-6, 13-1?13-2 s_m66en 3-2, 3-12, 4-4, 5-1, 5-2, 5-6 s_par 3-2, 3-12, 5-6, 14-3 s_par64 3-2, 3-13, 5-6, 6-38, 14-3, 17-2 s_perr# 3-2, 3-13, 5-6, 6-10, 12-1?12-13 s_pllen# 3-3, 3-17, 4-4, 5-6, 23-3 s_req[7:0]# 3-2, 5-6, 6-17, 14-1 s_req[7:1]# 3-13, 14-1 s_req0# 3-13, 14-1, 14-3 s_req64# 3-2, 3-14, 5-6 s_rstout# 3-18, 4-3, 4-4, 5-2, 5-3, 5-4, 5-6, 6-15, 6-17, 6-51, 20-1 s_serr# 3-2, 3-14, 6-14, 12-1, 12-5, 12-12?12-13 s_stop# 3-2, 3-14, 5-3, 5-6 s_trdy# 3-2, 3-14, 5-3, 5-6 s_tst[1:0] 3-22, 5-6 s_v io 3-4, 3-24, 5-6 s_xcap_in 3-23, 5-1, 5-6, 9-1 s_xcap_pu 3-23, 5-1, 5-6 sac 8-2, 9-2, 9-11, 10-3 secondary clock frequency measurement 4-6 clock pins 3-3, 3-16, 3-17, 3-21, 3-22, 4-1, 4-4, 4-6, 5-2, 20-1 flow-through control register 6-2, 6-26, 7-3 pci bus interface pins 3-2, 3-10?3-14 serial eeprom 6-2, 7-1?7-4 pins 3-3, 3-19 registers 5-7, 6-29?6-30 sftcr register 6-26, 7-3, 18-1, 18-2 signal specs 24-1?24-4 signaling voltage 3-24 sincpcnt register 6-23, 6-24, 7-3, 18-1, 18-3, 19-2, 19-4 single address cycle see sac sitlpcnt register 6-23, 6-24, 7-3, 18-1, 18-2, 19-2, 19-4 smart prefetch 6-27, 6-40?6-45, 19-3 smaxpcnt register 6-24, 6-25, 6-27, 7-3, 18-1, 18-3, 19-3 specs electrical 23-1 mechanical 24-1?24-4 split completion 9-1?9-20 spubard x registers 6-43?6-45 spul32bar1 register 6-41 spul32bar2 register 6-42 spul32bar3 register 6-43 spuu32bar1 register 6-42 spuu32bar2 register 6-42 spuu32bar3 register 6-43 system error event register 6-32 t tap controller see test access port controller target abort see abort, target tck 3-19, 22-1 tdi 3-19, 22-1, 22-2 tdo 3-19, 22-1, 22-2 termination, abnormal 13-2 test access port controller 22-1, 22-2
test register to v ss pci 6520cb data book, version 2.0 index-8 preliminary ? 2004 plx technology, inc. all rights reserved. test register 6-29 testability 22-1?22-2 timeout 19-3 control 6-2, 7-3 timeout control register 6-2, 6-19, 7-3, 8-4 timer registers 4-6, 6-15, 6-31 tmrcnt register 4-6, 6-31 tmrcntrl register 4-6, 6-31 tms 3-19, 22-1 tocntrl register 6-19, 6-32, 7-3, 8-4 transactions pci 8-1?8-18, 11-1?11-3 pci-x 9-1?9-22, 11-4?11-6 trst# 3-19, 22-1, 22-2 v v dd_core 3-24, 5-6 v dd_io 3-24, 5-6 vga 6-14, 10-1, 10-4, 10-4?10-5 vhdl 22-2 vhsic hardware description language 22-2 voltage signaling 3-24 vpd 21-1 registers 2-1, 6-49, 21-1 v ss 3-15, 3-17, 3-24, 5-6

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